{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T12:06:14Z","timestamp":1725797174314},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/patmos.2016.7833681","type":"proceedings-article","created":{"date-parts":[[2017,1,30]],"date-time":"2017-01-30T15:44:17Z","timestamp":1485791057000},"page":"155-161","source":"Crossref","is-referenced-by-count":6,"title":["Investigating PVT variability effects on full adders"],"prefix":"10.1109","author":[{"given":"Stephanie O.","family":"Ames","sequence":"first","affiliation":[]},{"given":"Vinicius","family":"Zanandrea","sequence":"additional","affiliation":[]},{"given":"Ingrid F. V.","family":"Oliveira","sequence":"additional","affiliation":[]},{"given":"Samuel P.","family":"Toledo","sequence":"additional","affiliation":[]},{"given":"Cristina","family":"Meinhardt","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.848806"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2009.02.001"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.4304\/jcp.3.2.48-54"},{"journal-title":"Digital Integrated Circuits A Design Perspective","year":"1996","author":"rabaey","key":"ref13"},{"journal-title":"Predictive technology models","year":"0","key":"ref14"},{"journal-title":"Ngspice","year":"0","key":"ref15"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2015455"},{"journal-title":"A Fine-grained Reconfigurable Logic Array based on double gate Transistors","year":"2002","author":"beckett","key":"ref3"},{"key":"ref6","article-title":"Analise de somadores de um bit trabalhando em baixo consumo de pot&#x00EA;ncia","author":"silva","year":"2011","journal-title":"Trabalho de Conclus&#x00E3;o de Curso \/ FURG"},{"key":"ref5","article-title":"A review of 0.18-&#x00B5;m full adder performances for tree structured arithmetic circuits","author":"chang","year":"2005","journal-title":"IEEE Trans on VLSI"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2014.0167"},{"key":"ref7","first-page":"418","article-title":"Design and analysis of robust dual threshold CMOS full adder circuit in 32 nm technology","author":"islam","year":"2010","journal-title":"Proc Int Conf Advances Recent Tech Comm And Computing (ARTCom)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.808446"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672005"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICRITO.2015.7359366"}],"event":{"name":"2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","start":{"date-parts":[[2016,9,21]]},"location":"Bremen, Germany","end":{"date-parts":[[2016,9,23]]}},"container-title":["2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7813533\/7833417\/07833681.pdf?arnumber=7833681","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,13]],"date-time":"2017-12-13T15:50:33Z","timestamp":1513180233000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7833681\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/patmos.2016.7833681","relation":{},"subject":[],"published":{"date-parts":[[2016,9]]}}}