{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T15:34:54Z","timestamp":1729611294264,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/patmos.2016.7833689","type":"proceedings-article","created":{"date-parts":[[2017,1,30]],"date-time":"2017-01-30T15:44:17Z","timestamp":1485791057000},"page":"205-212","source":"Crossref","is-referenced-by-count":1,"title":["PMHLS 2.0: An automated optimization of power management during high-level synthesis"],"prefix":"10.1109","author":[{"given":"Dominik","family":"Macko","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"37","article-title":"A very fast and quasi-accurate power-state-based system-level power modeling methodology","author":"xu","year":"2012","journal-title":"ARCS'12 Proceedings of the 25th international conference on architecture of computing systems"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/ISVLSI.2008.71"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.7873\/DATE.2013.327"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/ICECS.2011.6122376"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"53","DOI":"10.1007\/978-3-319-01418-0_4","article-title":"TLM POWER3: Power Estimation Methodology for SystemC TLM 2.0","volume":"265","author":"greaves","year":"2014","journal-title":"Models Methods and Tools for Complex Chip Design LNEE"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1007\/978-1-4020-9940-3_8"},{"key":"ref16","article-title":"High level power estimation and reduction techniques for power aware hardware design","author":"ahuja","year":"2010","journal-title":"Faculty of the Virginia Polytechnic Institute and State University"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1007\/978-94-007-1679-7_2"},{"year":"2011","journal-title":"ITRS","article-title":"The international technology roadmap for semiconductors: Design","key":"ref4"},{"year":"0","first-page":"1801","key":"ref3"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/DDECS.2015.16"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/VLSI-SoC.2015.7314393"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/PATMOS.2014.6951882"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/PATMOS.2013.6662154"},{"year":"2012","journal-title":"Power Forward","article-title":"Power Forward Initiative, A practical guide to low power design: User experience with CPF","key":"ref2"},{"year":"2007","author":"keating","journal-title":"Low Power Methodology for System-on-Chip Design","key":"ref1"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1049\/iet-cds.2011.0352"}],"event":{"name":"2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","start":{"date-parts":[[2016,9,21]]},"location":"Bremen, Germany","end":{"date-parts":[[2016,9,23]]}},"container-title":["2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7813533\/7833417\/07833689.pdf?arnumber=7833689","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,17]],"date-time":"2019-09-17T23:25:50Z","timestamp":1568762750000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7833689\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/patmos.2016.7833689","relation":{},"subject":[],"published":{"date-parts":[[2016,9]]}}}