{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T04:46:36Z","timestamp":1725597996623},"reference-count":28,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/patmos.2016.7833694","type":"proceedings-article","created":{"date-parts":[[2017,1,30]],"date-time":"2017-01-30T20:44:17Z","timestamp":1485809057000},"page":"243-249","source":"Crossref","is-referenced-by-count":1,"title":["Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI"],"prefix":"10.1109","author":[{"given":"Francisco","family":"Veirano","sequence":"first","affiliation":[]},{"given":"Lirida","family":"Naviner","sequence":"additional","affiliation":[]},{"given":"Fernando","family":"Silveira","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165578"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2005413"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5118319"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2015.10.001"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594240"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917505"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ECCTD.2011.6043407"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2013.6629305"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6571903"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MIEL.2014.6842076"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2631640"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.891726"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487798"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705356"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2169311"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014205"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852162"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1145\/1013235.1013265","article-title":"Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits","author":"calhoun","year":"2004","journal-title":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design LPE"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.837945"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2005.195479"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2002.1016866"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/EEEI.2014.7005822"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034476"},{"key":"ref21","article-title":"Low voltage logic circuits exploiting gate level dynamic body biasing in 28nm UTBB FD-SOI","author":"taco","year":"2015","journal-title":"Solid-State Electronics"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2014.6838617"},{"key":"ref23","first-page":"952","article-title":"UTBB FD-SOI: A Pro-cesslDesign Symbiosis for Breakthrough Energy-efficiency","author":"magarshack","year":"0"},{"key":"ref26","first-page":"1","article-title":"Performance analysis of multi- VT design solutions in 28nm UTBB FD-SOI technology","author":"pelloux-prayer","year":"2013","journal-title":"IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2155658"}],"event":{"name":"2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","start":{"date-parts":[[2016,9,21]]},"location":"Bremen, Germany","end":{"date-parts":[[2016,9,23]]}},"container-title":["2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7813533\/7833417\/07833694.pdf?arnumber=7833694","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,23]],"date-time":"2022-07-23T01:46:28Z","timestamp":1658540788000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7833694\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/patmos.2016.7833694","relation":{},"subject":[],"published":{"date-parts":[[2016,9]]}}}