{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,24]],"date-time":"2025-08-24T01:14:34Z","timestamp":1755998074724,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/patmos.2016.7833700","type":"proceedings-article","created":{"date-parts":[[2017,1,30]],"date-time":"2017-01-30T15:44:17Z","timestamp":1485791057000},"page":"283-288","source":"Crossref","is-referenced-by-count":9,"title":["A new bank sensitive DRAMPower model for efficient design space exploration"],"prefix":"10.1109","author":[{"given":"Matthias","family":"Jung","sequence":"first","affiliation":[]},{"given":"Deepak M.","family":"Mathew","sequence":"additional","affiliation":[]},{"given":"Eder F.","family":"Zulian","sequence":"additional","affiliation":[]},{"given":"Christian","family":"Weis","sequence":"additional","affiliation":[]},{"given":"Norbert","family":"Wehn","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742953"},{"key":"ref11","article-title":"Power Modelling of 3D-Stacked Memories with TLM2.0 based Virtual Platforms","author":"jung","year":"2013","journal-title":"SynopsysUser Group Conference (SNUG)"},{"key":"ref12","first-page":"1","article-title":"Ramulator: A Fast and Extensible DRAM Simulator","author":"kim","year":"2015","journal-title":"IEEE Computer Architecture Letters"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2432516.2432521"},{"journal-title":"Memory Systems Cache DRAM Disk","year":"2010","author":"jacob","key":"ref14"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjtsldm.8.63"},{"journal-title":"Drampower Open-source Dram Power & Energy Estimation Tool","year":"0","author":"chandrasekar","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488762"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"SIGARCH Comput Archit News"},{"journal-title":"The Datacenter as a Computer An Introduction to the Design of Warehouse-Scale Machines","year":"2009","author":"hoelzle","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2500727.2500734"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2011.17"},{"journal-title":"DDR3 SDRAM System-Power Calculator","year":"2014","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063482"}],"event":{"name":"2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","start":{"date-parts":[[2016,9,21]]},"location":"Bremen, Germany","end":{"date-parts":[[2016,9,23]]}},"container-title":["2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7813533\/7833417\/07833700.pdf?arnumber=7833700","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,17]],"date-time":"2019-09-17T23:25:51Z","timestamp":1568762751000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7833700\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/patmos.2016.7833700","relation":{},"subject":[],"published":{"date-parts":[[2016,9]]}}}