{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T07:38:05Z","timestamp":1725608285066},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.1109\/patmos.2017.8106978","type":"proceedings-article","created":{"date-parts":[[2017,11,16]],"date-time":"2017-11-16T21:50:40Z","timestamp":1510869040000},"page":"1-7","source":"Crossref","is-referenced-by-count":2,"title":["Prototyping memristors in digital system with an FPGA-based testing environment"],"prefix":"10.1109","author":[{"given":"Daniel","family":"Wust","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mehrdad","family":"Biglari","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Johannes","family":"Kncodtel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marc","family":"Reichenbach","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christopher","family":"Soll","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dietmar","family":"Fey","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ELINFOCOM.2016.7563016"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2645384"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865164"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2017.2682253"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2017.2682252"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1142\/S021812661450145X"},{"journal-title":"XADC Wizard v3 0","year":"0","author":"inc","key":"ref16"},{"journal-title":"Neuro-bit user manual","year":"0","key":"ref17"},{"journal-title":"Memristor","year":"0","key":"ref18"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2016.07.006"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1186\/1556-276X-9-526"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1088\/0268-1242\/29\/10\/104008"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/12.46283"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2989081.2989124"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2014.12.005"},{"key":"ref2","first-page":"1","article-title":"Design implications of memristor-based RRAM cross-point structures","author":"xu","year":"2011","journal-title":"Design Automation & Test in Europe Conference & Exhibition (DATE) 2011 IEEE"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2014.6880478"}],"event":{"name":"2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","start":{"date-parts":[[2017,9,25]]},"location":"Thessaloniki","end":{"date-parts":[[2017,9,27]]}},"container-title":["2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8095277\/8106944\/08106978.pdf?arnumber=8106978","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,18]],"date-time":"2017-12-18T23:04:36Z","timestamp":1513638276000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8106978\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/patmos.2017.8106978","relation":{},"subject":[],"published":{"date-parts":[[2017,9]]}}}