{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T01:55:15Z","timestamp":1725760515870},"reference-count":21,"publisher":"IEEE","license":[{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,7]]},"DOI":"10.1109\/patmos.2018.8463998","type":"proceedings-article","created":{"date-parts":[[2018,9,13]],"date-time":"2018-09-13T17:47:06Z","timestamp":1536860826000},"page":"147-154","source":"Crossref","is-referenced-by-count":1,"title":["Blade-OC Asynchronous Resilient Template"],"prefix":"10.1109","author":[{"given":"Moises","family":"Herrera","sequence":"first","affiliation":[]},{"given":"Tingyu","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Peter A.","family":"Beerel","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2220912"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2365878"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/12.2252"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/63526.63532"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1995.480191"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/43.720315"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511674730"},{"journal-title":"CMOS VLSI Design A Circuits and Systems Perspective","year":"2011","author":"weste","key":"ref17"},{"key":"ref18","article-title":"The advantages of latch-based design under process variation","author":"hurst","year":"2006","journal-title":"Int Workshop on Logic Synthesis (IWLS)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.860958"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2015.13"},{"key":"ref3","first-page":"110","article-title":"Performance and area optimization of a bundled-data intel processor through resynthesis","author":"saifhasherni","year":"2014","journal-title":"IEEE Symposium on Asynchronous Circuits and Systems (ASYNC)"},{"key":"ref6","first-page":"101","article-title":"Metastability in better-than-worst-case designs","author":"beer","year":"2014","journal-title":"IEEE Symposium on Asynchronous Circuits and Systems (ASYNC)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2015.60"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2036764"},{"key":"ref7","first-page":"61","article-title":"Performance optimization and analysis of blade designs under delay variability","author":"hand","year":"2015","journal-title":"IEEE Symposium on Asynchronous Circuits and Systems (ASYNC)"},{"key":"ref2","first-page":"19","article-title":"Ring oscillator clocks and margins","author":"cortadella","year":"2016","journal-title":"IEEE Symposium on Asynchronous Circuits and Systems (ASYNC)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007148"},{"key":"ref9","first-page":"21","article-title":"Sharp - a resilient asynchronous template","author":"waugaman","year":"2017","journal-title":"IEEE Symposium on Asynchronous Circuits and Systems (ASYNC)"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2014.320"},{"journal-title":"Plasma CPU","year":"2014","key":"ref21"}],"event":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","start":{"date-parts":[[2018,7,2]]},"location":"Platja d'Aro, Spain","end":{"date-parts":[[2018,7,4]]}},"container-title":["2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8450936\/8463989\/08463998.pdf?arnumber=8463998","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,3,22]],"date-time":"2022-03-22T15:53:10Z","timestamp":1647964390000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8463998\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/patmos.2018.8463998","relation":{},"subject":[],"published":{"date-parts":[[2018,7]]}}}