{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T05:51:57Z","timestamp":1747806717904,"version":"3.28.0"},"reference-count":30,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/perser.2005.1506430","type":"proceedings-article","created":{"date-parts":[[2005,9,12]],"date-time":"2005-09-12T11:19:24Z","timestamp":1126523964000},"page":"325-336","source":"Crossref","is-referenced-by-count":21,"title":["Implementing kilo-instruction multiprocessors"],"prefix":"10.1109","author":[{"given":"E.","family":"Vallejo","sequence":"first","affiliation":[]},{"given":"M.","family":"GalIuzzi","sequence":"additional","affiliation":[]},{"given":"A.","family":"CristaI","sequence":"additional","affiliation":[]},{"given":"F.","family":"Vallejo","sequence":"additional","affiliation":[]},{"given":"R.","family":"Beivide","sequence":"additional","affiliation":[]},{"given":"P.","family":"Stenstrom","sequence":"additional","affiliation":[]},{"given":"J.E.","family":"Smith","sequence":"additional","affiliation":[]},{"given":"M.","family":"Valero","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","article-title":"Token coherence: Decoupling performance and correctness","author":"martin","year":"2003","journal-title":"Proc of the 30th ISCA"},{"doi-asserted-by":"publisher","key":"17","DOI":"10.1109\/TC.1979.1675439"},{"key":"18","article-title":"On the value locality of store instructions","author":"lipasti","year":"2000","journal-title":"Proc of the 27th ISCA"},{"doi-asserted-by":"publisher","key":"15","DOI":"10.1145\/1024393.1024406"},{"key":"16","article-title":"A day in the life of a data cache miss","author":"karkhanis","year":"2002","journal-title":"Proc of the 2nd WMPI"},{"doi-asserted-by":"publisher","key":"13","DOI":"10.1145\/307338.300993"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1109\/ISCA.2004.1310767"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/ISCA.1990.134503"},{"key":"12","article-title":"Cache consistency and sequential consistency","volume":"61","author":"goodman","year":"1989","journal-title":"Technical Report No 61"},{"key":"21","article-title":"Speculative synchronization: Applying thread-level speculation to explicitly parallel applications","author":"marti?nez","year":"0","journal-title":"Proc ASPLOS X"},{"key":"20","article-title":"Ephemeral registers","author":"martinez","year":"2003","journal-title":"Technical Report"},{"key":"22","first-page":"186","article-title":"Delaying physical register allocation through virtual-physical registers","author":"monreal","year":"1999","journal-title":"Proc 30th Int l Symp Microarchitecture"},{"year":"2005","author":"moore","journal-title":"Thread-level Transactional Memory","key":"23"},{"doi-asserted-by":"publisher","key":"24","DOI":"10.1109\/HPCA.2003.1183532"},{"doi-asserted-by":"publisher","key":"25","DOI":"10.1145\/237090.237142"},{"doi-asserted-by":"publisher","key":"26","DOI":"10.1109\/MICRO.2001.991127"},{"key":"27","article-title":"Transactional lock-free execution of lock-based programs","author":"rajwar","year":"0","journal-title":"Proc ASPLOS X"},{"key":"28","article-title":"Using speculative retirement and larger instruction window to narrow the performance gap between memory consistency models","author":"ranganathan","year":"1997","journal-title":"Proceedings of Symposium on Parallelism in Algorithms and Architectures"},{"key":"29","article-title":"Speculative lock reordering","author":"rundberg","year":"2003","journal-title":"Proc of IPDPS"},{"key":"3","first-page":"2","article-title":"A case for resource-conscious out-of-order processors","author":"cristal","year":"2003","journal-title":"IEEE TCCA Comp Architecture Letters"},{"key":"2","article-title":"Large virtual ROBs by processor checkpointing","volume":"upc dac 2002 39","author":"cristal","year":"2002","journal-title":"Tech Rep"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1145\/977091.977120"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/HPCA.2005.41"},{"key":"30","article-title":"SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint\/recovery","author":"sorin","year":"2002","journal-title":"Proc of the 30th ISCA"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/MM.2005.53"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1145\/1044823.1044825"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/HPCA.2004.10008"},{"key":"4","article-title":"Kilo-instruction processors","volume":"2858","author":"cristal","year":"2003","journal-title":"LNCS"},{"key":"9","first-page":"119","article-title":"Internal organization of the alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor","volume":"7","author":"edmondson","year":"1995","journal-title":"Digital Technical Journal"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/ISCA.1994.288150"}],"event":{"name":"ICPS '05. International Conference on Pervasive Services, 2005.","location":"Santorini, Greece"},"container-title":["ICPS '05. Proceedings. International Conference on Pervasive Services, 2005."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10064\/32279\/01506430.pdf?arnumber=1506430","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T21:36:38Z","timestamp":1489527398000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1506430\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/perser.2005.1506430","relation":{},"subject":[]}}