{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T03:13:48Z","timestamp":1729653228838,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/prdc.2004.1276583","type":"proceedings-article","created":{"date-parts":[[2004,6,10]],"date-time":"2004-06-10T10:19:45Z","timestamp":1086862785000},"page":"327-332","source":"Crossref","is-referenced-by-count":13,"title":["Evaluation of fault-tolerant designs implemented on SRAM-based FPGAs"],"prefix":"10.1109","author":[{"given":"G.","family":"Asadi","sequence":"first","affiliation":[]},{"given":"S.G.","family":"Miremadi","sequence":"additional","affiliation":[]},{"given":"H.R.","family":"Zarandi","sequence":"additional","affiliation":[]},{"given":"A.","family":"Ejlali","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/23.556861"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2002.1167533"},{"key":"17","article-title":"Single event upset mitigation techniques for SRAM-based FPGAs","author":"lima","year":"2003","journal-title":"Proceedings of the 4th IEEE Latin-American Test Workshop (LATW'03)"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766651"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2000.887182"},{"key":"16","article-title":"A fault injection analysis of virtex FPGA TMR design methodology","author":"lima","year":"2001","journal-title":"Proc Radiation Effects Components and Systems Conf"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1994.315656"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/12.364536"},{"key":"11","doi-asserted-by":"crossref","first-page":"724","DOI":"10.1109\/43.712103","article-title":"Sequential circuit fault simulation using logic emulation","volume":"17","author":"hwang","year":"1998","journal-title":"IEEE Trans Computer-Aided Design"},{"key":"12","article-title":"Experimental analysis of computer system dependability","author":"iyer","year":"1996","journal-title":"Fault-Tolerant Computer System Design"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041811"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/32.44380"},{"key":"20","article-title":"Simulation-based analysis of SEU effects on SRAM-based FPGAs","author":"rebaudengo","year":"2002","journal-title":"Proc 12th Int Conf Field-Programmable Logic and Applications"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2000.887181"},{"journal-title":"Altera Flex10KE Datasheet","article-title":"Flex 10KE embedded programmable logic family","year":"1999","key":"1"},{"key":"10","article-title":"Radiation characterization and SEU mitigation of the virtex FPGA for space-based reconfigurable computing","author":"fuller","year":"2000","journal-title":"Proc IEEE Nuclear and Space Radiation Effects Conf (NSREC)"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/43.790625"},{"key":"6","article-title":"Proton testing of SEU mitigation methods for the virtex FPGA","author":"carmichael","year":"2001","journal-title":"Proceedings of the Military and Aerospace Applications of Programmable Logic Devices (MAPLD)"},{"key":"5","article-title":"Correcting single event upsets through virtex partial reconfiguration","volume":"216","author":"carmichael","year":"2000","journal-title":"Xilinx Application Notes"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041812"},{"key":"9","first-page":"479","article-title":"A hybrid fault injection approach based on simulation and emulation co-operation","author":"ejlai","year":"2003","journal-title":"Proceedings of the IEEE International Conference on Dependable Systems and Networks (DSN-2003)"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"}],"event":{"name":"10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004.","location":"Papeete, Tahiti, French Polynesia"},"container-title":["10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8995\/28541\/01276583.pdf?arnumber=1276583","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T03:56:23Z","timestamp":1497585383000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1276583\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/prdc.2004.1276583","relation":{},"subject":[]}}