{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,31]],"date-time":"2025-07-31T00:38:43Z","timestamp":1753922323033},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,7]]},"DOI":"10.1109\/prime.2019.8787743","type":"proceedings-article","created":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T01:18:06Z","timestamp":1565054286000},"source":"Crossref","is-referenced-by-count":5,"title":["A Generic Procedural Generator for Sizing of Analog Integrated Circuits"],"prefix":"10.1109","author":[{"given":"Matthias","family":"Schweikardt","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yannick","family":"Uhlmann","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Florian","family":"Leber","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jurgen","family":"Scheible","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Husni","family":"Habal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","year":"0"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351731"},{"key":"ref12","first-page":"113","author":"blei","year":"2006","journal-title":"Dynamic topic models Proc Int Conf Machine Learning (ICML06)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1609\/aimag.v13i3.1011"},{"key":"ref4","first-page":"33","article-title":"Automation of Analog IC Layout Challenges and Solutions","author":"scheible","year":"2015","journal-title":"Proc of Int Symp on Physical Design (ISPD’15)"},{"key":"ref3","year":"0"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052861"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2003.1194751"},{"key":"ref8","author":"allen","year":"2002","journal-title":"CMOS Analog Circuit Design"},{"key":"ref7","article-title":"PROFET™+ Benchmark Robustness and Diagnostics in Modular Packages, Infineon Technologies AG, 85579 Neubiberg, Germany, 2011, Order Number: B127-H9640-X-X-7600","year":"0"},{"key":"ref2","year":"0","journal-title":"WickeD Manual for WickeD ™ 6 8 MunEDA GmbH"},{"key":"ref1","first-page":"1","article-title":"A Procedural Approach to Automate the Manual Design Process in Analog Integrated Circuit Design","author":"leber","year":"2018","journal-title":"ANALOG 2018 16th GMM\/ITG-Symposium dummydata"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1017\/9781108125840"}],"event":{"name":"2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","location":"Lausanne, Switzerland","start":{"date-parts":[[2019,7,15]]},"end":{"date-parts":[[2019,7,18]]}},"container-title":["2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8777448\/8787731\/08787743.pdf?arnumber=8787743","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,17]],"date-time":"2022-07-17T21:48:36Z","timestamp":1658094516000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8787743\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,7]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/prime.2019.8787743","relation":{},"subject":[],"published":{"date-parts":[[2019,7]]}}}