{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T01:07:36Z","timestamp":1725412056523},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,12]]},"DOI":"10.1109\/reconfig.2012.6416731","type":"proceedings-article","created":{"date-parts":[[2013,1,30]],"date-time":"2013-01-30T17:52:35Z","timestamp":1359568355000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["An implementation of a directory protocol for a cache coherent system on FPGAs"],"prefix":"10.1109","author":[{"given":"Vincent","family":"Mirian","sequence":"first","affiliation":[]},{"given":"Paul","family":"Chow","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","first-page":"321","article-title":"In-network cache coherence","author":"eisley","year":"2006","journal-title":"Proceedings of the 39th Annual IEEE\/ACM International Symposium on Microarchitecture"},{"journal-title":"Coherent Shared Memories for FPGAs","year":"2009","author":"woods","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1988.5238"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/2.55497"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339696"},{"journal-title":"The Hardware\/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design)","year":"2008","author":"patterson","key":"2"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412109"},{"journal-title":"Block RAM (BRAM) Block (v1 00a)","year":"2009","author":"hum","key":"10"},{"journal-title":"LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2 11e)","year":"2011","key":"7"},{"journal-title":"Intel's 64 and IA-32 Architectures Software Developer's Manual Specification","year":"2007","key":"6"},{"journal-title":"Forward State for Use in Cache Coherency in A Multiprocessor System","year":"2005","author":"hum","key":"5"},{"year":"0","key":"4"},{"journal-title":"Memory Interface Solutions","year":"2010","author":"hum","key":"9"},{"journal-title":"Local Memory Bus (LMB) V10 (v2 00 b)","year":"2011","author":"hum","key":"8"}],"event":{"name":"2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2012)","start":{"date-parts":[[2012,12,5]]},"location":"Cancun, Mexico","end":{"date-parts":[[2012,12,7]]}},"container-title":["2012 International Conference on Reconfigurable Computing and FPGAs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6410219\/6416717\/06416731.pdf?arnumber=6416731","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T16:14:50Z","timestamp":1490112890000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6416731\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,12]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/reconfig.2012.6416731","relation":{},"subject":[],"published":{"date-parts":[[2012,12]]}}}