{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T10:14:05Z","timestamp":1729678445456,"version":"3.28.0"},"reference-count":25,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,12]]},"DOI":"10.1109\/reconfig.2012.6416736","type":"proceedings-article","created":{"date-parts":[[2013,1,30]],"date-time":"2013-01-30T22:52:35Z","timestamp":1359586355000},"page":"1-6","source":"Crossref","is-referenced-by-count":12,"title":["Design and analysis of layered coarse-grained reconfigurable architecture"],"prefix":"10.1109","author":[{"given":"Zoltan Endre","family":"Rakossy","sequence":"first","affiliation":[]},{"given":"Tejas","family":"Naphade","sequence":"additional","affiliation":[]},{"given":"Anupam","family":"Chattopadhyay","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"19","DOI":"10.1109\/TC.1985.1676516"},{"doi-asserted-by":"publisher","key":"17","DOI":"10.1109\/12.90254"},{"doi-asserted-by":"publisher","key":"18","DOI":"10.1016\/S0898-1221(97)00028-X"},{"year":"1997","author":"corporaal","journal-title":"Microprocessor Architectures From VLIW to TTA","key":"15"},{"doi-asserted-by":"publisher","key":"16","DOI":"10.1109\/TVLSI.2008.2009352"},{"doi-asserted-by":"publisher","key":"13","DOI":"10.1109\/AHS.2007.34"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1109\/SPL.2007.371750"},{"key":"11","doi-asserted-by":"crossref","first-page":"171","DOI":"10.1007\/978-3-642-11515-8_14","article-title":"Memory-aware application mapping on coarse-grained reconfigurable arrays","author":"kim","year":"2010","journal-title":"High Performance Embedded Architectures and Compilers"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/RECONF.2006.307777"},{"key":"21","volume":"3","author":"golub","year":"1996","journal-title":"Matrix Computations"},{"doi-asserted-by":"publisher","key":"20","DOI":"10.1145\/1127908.1127979"},{"year":"0","key":"22"},{"doi-asserted-by":"publisher","key":"23","DOI":"10.1145\/1188275.1188276"},{"doi-asserted-by":"publisher","key":"24","DOI":"10.1109\/TC.2012.209"},{"doi-asserted-by":"publisher","key":"25","DOI":"10.1155\/2007\/87046"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/FCCM.2012.22"},{"key":"2","article-title":"Architecture exploration for a reconfigurable architecture template","author":"mei","year":"2005","journal-title":"Design & Test of Computers"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/2.612254"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/2.839320"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/TVLSI.2008.2002685"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1145\/2003695.2003702"},{"year":"0","key":"5"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/FPGA.1996.564808"},{"year":"0","key":"9"},{"year":"0","key":"8"}],"event":{"name":"2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2012)","start":{"date-parts":[[2012,12,5]]},"location":"Cancun, Mexico","end":{"date-parts":[[2012,12,7]]}},"container-title":["2012 International Conference on Reconfigurable Computing and FPGAs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6410219\/6416717\/06416736.pdf?arnumber=6416736","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T06:42:24Z","timestamp":1498027344000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6416736\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,12]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/reconfig.2012.6416736","relation":{},"subject":[],"published":{"date-parts":[[2012,12]]}}}