{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,26]],"date-time":"2025-08-26T00:15:34Z","timestamp":1756167334668,"version":"3.44.0"},"reference-count":20,"publisher":"IEEE","license":[{"start":{"date-parts":[[2012,12,1]],"date-time":"2012-12-01T00:00:00Z","timestamp":1354320000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2012,12,1]],"date-time":"2012-12-01T00:00:00Z","timestamp":1354320000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,12]]},"DOI":"10.1109\/reconfig.2012.6416753","type":"proceedings-article","created":{"date-parts":[[2013,1,30]],"date-time":"2013-01-30T17:52:35Z","timestamp":1359568355000},"page":"1-7","source":"Crossref","is-referenced-by-count":9,"title":["Hardware design and implementation of a Network-on-Chip based load balancing switch fabric"],"prefix":"10.1109","author":[{"given":"Turhan","family":"Karadeniz","sequence":"first","affiliation":[{"name":"Computer Engineering Department, University of California Santa Cruz"}]},{"given":"Lotfi","family":"Mhamdi","sequence":"additional","affiliation":[{"name":"School of Electronic and Electrical Engineering, University of Leeds, UK"}]},{"given":"Kees","family":"Goossens","sequence":"additional","affiliation":[{"name":"Electrical Engineering Faculty, Technical University of Eindhoven, Netherlands"}]},{"given":"J.J.","family":"Garcia-Luna-Aceves","sequence":"additional","affiliation":[{"name":"Computer Engineering Department, University of California Santa Cruz"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/CNSR.2010.18"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/CSICC.2009.5349425"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2009.211"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380772"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2008.4746257"},{"key":"13","doi-asserted-by":"crossref","first-page":"1226","DOI":"10.1109\/DATE.2005.36","article-title":"A router architecture for connection-oriented service guarantees in the MANGO clock-less network-on-chip","volume":"2","author":"bjerregaard","year":"2005","journal-title":"Design Automation and Test in Europe 2005 Proceedings"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCS.2005.1511290"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2003.1240952"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2008.5213921"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ICC.1989.49679"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1987.1676939"},{"key":"2","first-page":"423","article-title":"A new bus assignment in a designed shared bus switch fabric,\" in Circuits and Systems","volume":"1","author":"torres","year":"1999","journal-title":"1999 ISCAS '99 Proceedings of the 1999 IEEE International Symposium on"},{"journal-title":"The Tiny Tera A Packet Switch Core","year":"1996","author":"mckeown","key":"1"},{"key":"10","doi-asserted-by":"crossref","first-page":"890","DOI":"10.1109\/DATE.2004.1269001","article-title":"Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip","volume":"2","author":"millberg","year":"2004","journal-title":"Design Automation and Test in Europe Conference and Exhibition 2004 Proceedings"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/90.769767"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1016\/S0169-7552(98)00157-3"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/161541.161736"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.65"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.99"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/INFCOM.2005.1498452"}],"event":{"name":"2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2012)","start":{"date-parts":[[2012,12,5]]},"location":"Cancun, Mexico","end":{"date-parts":[[2012,12,7]]}},"container-title":["2012 International Conference on Reconfigurable Computing and FPGAs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6410219\/6416717\/06416753.pdf?arnumber=6416753","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,25]],"date-time":"2025-08-25T20:17:27Z","timestamp":1756153047000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6416753\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,12]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/reconfig.2012.6416753","relation":{},"subject":[],"published":{"date-parts":[[2012,12]]}}}