{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,24]],"date-time":"2025-08-24T01:38:53Z","timestamp":1755999533192},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,12]]},"DOI":"10.1109\/reconfig.2012.6416785","type":"proceedings-article","created":{"date-parts":[[2013,1,30]],"date-time":"2013-01-30T17:52:35Z","timestamp":1359568355000},"page":"1-6","source":"Crossref","is-referenced-by-count":11,"title":["Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA"],"prefix":"10.1109","author":[{"given":"U.","family":"Kretzschmar","sequence":"first","affiliation":[]},{"given":"A.","family":"Astarloa","sequence":"additional","affiliation":[]},{"given":"J.","family":"Lazaro","sequence":"additional","affiliation":[]},{"given":"M.","family":"Garay","sequence":"additional","affiliation":[]},{"given":"J.","family":"Del Ser","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores Revision B 3","year":"2002","key":"13"},{"journal-title":"ML505\/ML506\/ML507 Evaluation Platform User Guide","year":"2009","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2004.1319668"},{"year":"2010","key":"12"},{"journal-title":"Triple Module Redundancy Design Techniques for Virtex FPGAs","year":"0","author":"carmichael","key":"3"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2005.856543"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.16"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2003.1250097"},{"key":"7","article-title":"Virtex-5 seu critical bit information extending the capability of the virtex-5 seu controller","author":"chapman","year":"0","journal-title":"Xilinx Documentation SEU Lounge"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2011.6089684"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2006.251221"},{"key":"4","first-page":"1","article-title":"Partitioning triple modular redundancy for single event upset mitigation in fpga","author":"wang","year":"2010","journal-title":"2010 International Conference on EProduct E-Service and E-Entertainment (ICEEE)"},{"key":"9","article-title":"Fault injection into sram-based fpga for the analysis of seu effects","author":"baker","year":"2003","journal-title":"IEEE International Conference on Field-Programmable Technology (FPT)"},{"journal-title":"Xilinx-5 FPGA Configuration User Guide","year":"2010","key":"8"}],"event":{"name":"2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2012)","start":{"date-parts":[[2012,12,5]]},"location":"Cancun, Mexico","end":{"date-parts":[[2012,12,7]]}},"container-title":["2012 International Conference on Reconfigurable Computing and FPGAs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6410219\/6416717\/06416785.pdf?arnumber=6416785","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T16:38:21Z","timestamp":1490114301000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6416785\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,12]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/reconfig.2012.6416785","relation":{},"subject":[],"published":{"date-parts":[[2012,12]]}}}