{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T04:40:13Z","timestamp":1729658413143,"version":"3.28.0"},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,12]]},"DOI":"10.1109\/reconfig.2013.6732274","type":"proceedings-article","created":{"date-parts":[[2014,2,10]],"date-time":"2014-02-10T11:26:59Z","timestamp":1392031619000},"page":"1-6","source":"Crossref","is-referenced-by-count":13,"title":["Countermeasures against EM analysis for a secured FPGA-based AES implementation"],"prefix":"10.1109","author":[{"given":"P.","family":"Maistri","sequence":"first","affiliation":[]},{"given":"S.","family":"Tiran","sequence":"additional","affiliation":[]},{"given":"P.","family":"Maurine","sequence":"additional","affiliation":[]},{"given":"I.","family":"Koren","sequence":"additional","affiliation":[]},{"given":"R.","family":"Leveugle","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","article-title":"Parallel FPGA implementation of RSA with residue number systems-can side-channel threats be avoided","author":"ciet","year":"2003","journal-title":"MWSCAS'2003"},{"journal-title":"Recommendation for Block Cipher Modes of Operation","year":"2001","key":"22"},{"key":"17","first-page":"142","article-title":"More dual rijndaels","volume":"3373","author":"raddum","year":"2004","journal-title":"AES Conference 2004"},{"key":"23","first-page":"443","article-title":"A unified framework for the analysis of side-channel key recovery attacks","volume":"5479","author":"standaert","year":"2009","journal-title":"Eurocrypt"},{"journal-title":"Efficient VLSI architectures for bit-parallel computation in Galois fields","year":"1994","author":"paar","key":"18"},{"key":"15","first-page":"171","article-title":"Efficient rijndael encryption implementation with composite field arithmetic","author":"rudra","year":"2001","journal-title":"CHES"},{"key":"16","doi-asserted-by":"crossref","first-page":"160","DOI":"10.1007\/3-540-36178-2_10","article-title":"How many ways can you write rijndael?","volume":"2501","author":"barkan","year":"2002","journal-title":"Asiacrypt 2002"},{"key":"13","first-page":"239","article-title":"A compact rijndael hardware architecture with s-box optimization","author":"satoh","year":"2001","journal-title":"ASIACRYPT"},{"journal-title":"Spartan-3 FPGA Family Data Sheet","year":"2009","key":"14"},{"key":"11","first-page":"28","article-title":"Random register renaming to foil dpa","author":"may","year":"2001","journal-title":"CHES 2001 LNCS 2162"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2010.5642612"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-04101-3"},{"key":"3","first-page":"16","article-title":"Correlation power analysis with a leakage model","author":"brier","year":"2004","journal-title":"CHES"},{"key":"20","first-page":"198","article-title":"Multiplicative masking and power analysis of aes","author":"golic?","year":"2003","journal-title":"CHES 2002"},{"key":"2","first-page":"388","article-title":"Differential power analysis","author":"kocher","year":"1999","journal-title":"Crypto"},{"journal-title":"FIPS-197 Advanced Encryption Standard","year":"2001","key":"1"},{"key":"10","first-page":"98","article-title":"Efficient aes implementations on asics and fpgas","author":"pramstaller","year":"2004","journal-title":"Fourth Int'l Conf Advanced Encryption Standard (AES '04)"},{"key":"7","first-page":"238","article-title":"Using second-order power analysis to attack dpa resistant software","volume":"1965","author":"messerges","year":"2001","journal-title":"CHES"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-04138-9_12"},{"journal-title":"Power Analysis Attacks-revealing the Secrets of Smart Cards","year":"2007","author":"mangard","key":"5"},{"key":"4","first-page":"200","article-title":"Electromagnetic analysis (EMA): Measures and counter-measures for smard cards","volume":"2140","author":"quisquater","year":"2001","journal-title":"E-smart'2001"},{"key":"9","first-page":"172","article-title":"Masked dual-rail pre-charge logic: Dparesistance without routing constraints","author":"popp","year":"2005","journal-title":"CHES"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268856"}],"event":{"name":"2013 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","start":{"date-parts":[[2013,12,9]]},"location":"Cancun, Mexico","end":{"date-parts":[[2013,12,11]]}},"container-title":["2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6720231\/6732246\/06732274.pdf?arnumber=6732274","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T03:36:32Z","timestamp":1498102592000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6732274\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/reconfig.2013.6732274","relation":{},"subject":[],"published":{"date-parts":[[2013,12]]}}}