{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T22:17:48Z","timestamp":1729635468718,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,12]]},"DOI":"10.1109\/reconfig.2014.7032496","type":"proceedings-article","created":{"date-parts":[[2015,2,11]],"date-time":"2015-02-11T22:18:50Z","timestamp":1423693130000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["An adaptive victim cache scheme"],"prefix":"10.1109","author":[{"given":"Osvaldo","family":"Navarro","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Hubner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"509","DOI":"10.1109\/92.931228","article-title":"A reconfigurable multifunction computing cache architecture","volume":"9","author":"kim","year":"2001","journal-title":"Very Large Scale Integration (VLSI) Systems IEEE Transactions on"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"364","DOI":"10.1109\/ISCA.1990.134547","article-title":"Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers","author":"jouppi","year":"1990","journal-title":"Computer Architecture 1990 Proceedings 17th"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/UIC-ATC.2012.36"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854333"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/40.755465"},{"article-title":"Sim-alpha: a validated, execution-driven alpha 21264 simulator","year":"2001","author":"doug","key":"ref3"},{"key":"ref6","article-title":"Cacti 2. 0: An integrated cache timing and power model","author":"reinman","year":"2000","journal-title":"Wester Research Laboratory Research Report"},{"key":"ref5","first-page":"3","article-title":"Mibench: A free, commercially representative embedded benchmark suite","author":"guthaus","year":"2001","journal-title":"Workload Characterization 2001 WWC-4 2001 IEEE International Workshop on"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1795194.1795218"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/993396.993405"},{"key":"ref2","first-page":"1","article-title":"A survey of architectural techniques for improving cache power efficiency","author":"mittal","year":"2013","journal-title":"Sustainable Computing Informatics and Systems"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859635"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICESS.Symposia.2008.84"}],"event":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","start":{"date-parts":[[2014,12,8]]},"location":"Cancun, Mexico","end":{"date-parts":[[2014,12,10]]}},"container-title":["2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7012990\/7032472\/07032496.pdf?arnumber=7032496","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,29]],"date-time":"2020-08-29T22:48:32Z","timestamp":1598741312000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7032496\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,12]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/reconfig.2014.7032496","relation":{},"subject":[],"published":{"date-parts":[[2014,12]]}}}