{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T08:07:08Z","timestamp":1729670828396,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,12]]},"DOI":"10.1109\/reconfig.2014.7032554","type":"proceedings-article","created":{"date-parts":[[2015,2,11]],"date-time":"2015-02-11T17:18:50Z","timestamp":1423675130000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Rotated parallel mapping: A novel approach for mapping data parallel applications on CGRAs"],"prefix":"10.1109","author":[{"given":"Simon","family":"Schulz","sequence":"first","affiliation":[]},{"given":"Oliver","family":"Bringmann","sequence":"additional","affiliation":[]},{"given":"Thomas","family":"Schweizer","sequence":"additional","affiliation":[]},{"given":"Wolfgang","family":"Rosenstiel","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-05960-0_29"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1524\/itit.2007.49.3.157"},{"journal-title":"Synthesis and Optimization of Digital Circuits","year":"1994","author":"micheli","key":"ref12"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"671","DOI":"10.1126\/science.220.4598.671","article-title":"Optimization by simulated annealing","volume":"220","author":"kirkpatrick","year":"1983","journal-title":"Science"},{"key":"ref14","article-title":"Cost functions for the design of dynamically reconfigurable processor architectures","author":"oppold","year":"2004","journal-title":"Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1531542.1531555"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2012.39"},{"key":"ref6","first-page":"166","article-title":"Dresc: a retargetable compiler for coarse-grained reconfigurable architectures","author":"mei","year":"2002","journal-title":"FPT"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253623"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488756"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454140"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370535"},{"key":"ref9","first-page":"616","article-title":"A data prefetch and reuse strategy for coarse-grained reconfigurable architectures","volume":"96","author":"wei","year":"2013","journal-title":"IEICE Transactions on Information and Systems"}],"event":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","start":{"date-parts":[[2014,12,8]]},"location":"Cancun, Mexico","end":{"date-parts":[[2014,12,10]]}},"container-title":["2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7012990\/7032472\/07032554.pdf?arnumber=7032554","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T01:21:54Z","timestamp":1498180914000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7032554\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,12]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/reconfig.2014.7032554","relation":{},"subject":[],"published":{"date-parts":[[2014,12]]}}}