{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,24]],"date-time":"2025-11-24T12:35:13Z","timestamp":1763987713018},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,12]]},"DOI":"10.1109\/reconfig.2015.7393282","type":"proceedings-article","created":{"date-parts":[[2016,2,1]],"date-time":"2016-02-01T22:58:27Z","timestamp":1454367507000},"page":"1-6","source":"Crossref","is-referenced-by-count":8,"title":["A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms"],"prefix":"10.1109","author":[{"given":"Omar W.","family":"Ibraheem","sequence":"first","affiliation":[]},{"given":"Arif","family":"Irwansyah","sequence":"additional","affiliation":[]},{"given":"Jens","family":"Hagemeyer","sequence":"additional","affiliation":[]},{"given":"Mario","family":"Porrmann","sequence":"additional","affiliation":[]},{"given":"Ulrich","family":"Rueckert","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Standard Specification","article-title":"CoaXPress Standard V1.1","year":"2013","key":"ref10"},{"journal-title":"Interface Standard Specifications","article-title":"Camera Link HS V1.0","year":"2012","key":"ref11"},{"journal-title":"Standard Specification","article-title":"GigE Vision, Video Streaming and Device Control over Ethernet Standard v2.0","year":"2012","key":"ref12"},{"journal-title":"Standard Specification","article-title":"USB3 Vision V1.0","year":"2013","key":"ref13"},{"journal-title":"GigE Vision Reference Design for Reciever Devices","year":"2013","key":"ref14"},{"journal-title":"LogiCORE IP XPS LL TEMAC (v2 03a) Datasheet","year":"2010","key":"ref15"},{"year":"2014","key":"ref16","article-title":"GigE Vision - True Plug and Play Connectivity"},{"key":"ref17","first-page":"592","article-title":"RAPTOR - A Scalable Platform for Rapid Prototyping and FPGA-based Cluster Computing","author":"porrmann","year":"2010","journal-title":"Parallel Computing From Multicores and GPU's to Petascale Advances in Parallel Computing"},{"journal-title":"LogiCORE IP Multi-Port Memory Controller (v6 05 a) Datasheet (DS643)","year":"2011","key":"ref18"},{"key":"ref19","article-title":"A simple gray-edge automatic white balance method with FPGA implmentation","author":"tan","year":"2013","journal-title":"Journal of Real-Time Image Processing"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IROS.2013.6696733"},{"journal-title":"White Paper","article-title":"Vision-Critical Networked Video","year":"2012","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/EIT.2010.5612173"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.179"},{"journal-title":"Spartan-6 Industrial Video Processing Kit - EDK Reference Design Tutorial","year":"2010","key":"ref8"},{"key":"ref7","article-title":"An FPGA-based Smart Camera System","author":"said","year":"2013","journal-title":"proceeding of Third International IEEE Conference (IPWIS'13)"},{"journal-title":"The GigE Vision&#x00AE; Interface Standard Transforming Medical Imaging","year":"2012","author":"phillips","key":"ref2"},{"key":"ref1","first-page":"1133","article-title":"Smart surveillance: applications, technologies and implications","author":"hampapur","year":"2003","journal-title":"Proc of Fourth IEEE Pacific-Rim Conf on Multimedia (ICICS-PCM '03)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2013.2290576"},{"key":"ref20","article-title":"White point estimation for uncalibrated images","author":"cardei","year":"1999","journal-title":"Proceedings of the IS and T\/SID seventh color imaging conference color science systems and applications"}],"event":{"name":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","start":{"date-parts":[[2015,12,7]]},"location":"Riviera Maya, Mexico","end":{"date-parts":[[2015,12,9]]}},"container-title":["2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7390332\/7393279\/07393282.pdf?arnumber=7393282","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T21:37:54Z","timestamp":1490132274000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7393282\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/reconfig.2015.7393282","relation":{},"subject":[],"published":{"date-parts":[[2015,12]]}}}