{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T12:50:25Z","timestamp":1730292625972,"version":"3.28.0"},"reference-count":30,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,12]]},"DOI":"10.1109\/reconfig.2018.8641724","type":"proceedings-article","created":{"date-parts":[[2019,2,14]],"date-time":"2019-02-14T23:39:16Z","timestamp":1550187556000},"page":"1-8","source":"Crossref","is-referenced-by-count":1,"title":["Post-Routing Analytical Wirelength Model for Homogeneous FPGA Architectures"],"prefix":"10.1109","author":[{"given":"Arpit","family":"Soni","sequence":"first","affiliation":[]},{"given":"Yoon Kah","family":"Leow","sequence":"additional","affiliation":[]},{"given":"Ali","family":"Akoglu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","article-title":"Negotiated a* routing for fpgas","author":"tessier","year":"1998","journal-title":"Proc Canadian Workshop Field-Programmable Devices"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2011.6132683"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223159"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2009.5377673"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2004.1261040"},{"article-title":"Post-routing analytical models for homogeneous fpga architectures","year":"2013","author":"leow","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1675882"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"580","DOI":"10.1109\/16.661219","article-title":"a stochastic wire-length distribution for gigascale integration (gsi). i. derivation and validation","volume":"45","author":"davis","year":"1998","journal-title":"IEEE Transactions on Electron Devices"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/16.661220"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1981.1084958"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887922"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1137\/0130013"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950449"},{"key":"ref27","first-page":"171","article-title":"Cross-validation, the bayes theorem, and smallsample bias","volume":"8","author":"allenby","year":"2007","journal-title":"Journal of Business and Economic Statistics"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/43.251146"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344694"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/611817.611844"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2499625.2499627"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2079339"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272519"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2629579"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508156"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645503"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145708"},{"key":"ref22","article-title":"Efficient fpga mapping using priority cuts","author":"cho","year":"2007","journal-title":"Proc FPGA"},{"article-title":"A system-level synthetic circuit generator for fpga architectural analysis","year":"2008","author":"mark","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296426"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159755"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1080\/00401706.1977.10489581"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"}],"event":{"name":"2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","start":{"date-parts":[[2018,12,3]]},"location":"Cancun, Mexico","end":{"date-parts":[[2018,12,5]]}},"container-title":["2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8637084\/8641689\/08641724.pdf?arnumber=8641724","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T08:00:26Z","timestamp":1643270426000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8641724\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,12]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/reconfig.2018.8641724","relation":{},"subject":[],"published":{"date-parts":[[2018,12]]}}}