{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,9]],"date-time":"2025-04-09T06:48:16Z","timestamp":1744181296573},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,12]]},"DOI":"10.1109\/reconfig48160.2019.8994693","type":"proceedings-article","created":{"date-parts":[[2020,2,14]],"date-time":"2020-02-14T08:23:28Z","timestamp":1581668608000},"page":"1-8","source":"Crossref","is-referenced-by-count":7,"title":["Seiba: An FPGA Overlay-Based Approach to Rapid Application Development"],"prefix":"10.1109","author":[{"given":"David","family":"Wilson","sequence":"first","affiliation":[]},{"given":"Greg","family":"Stitt","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00076"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2015.49"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2514740"},{"key":"ref6","first-page":"31","article-title":"A Soft Processor Overlay with Tightly-coupled FPGA Accelerator","author":"ng","year":"2016","journal-title":"2nd International Workshop On Overlay Architecture For FPGAs (LOAF)"},{"key":"ref11","first-page":"170","author":"panda","year":"2004","journal-title":"1995 high level synthesis design repository"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039376"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174247"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3241793.3241797"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DASC-PICom-DataCom-CyberSciTec.2016.110"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00022"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.21236\/ADA492273"}],"event":{"name":"2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","start":{"date-parts":[[2019,12,9]]},"location":"Cancun, Mexico","end":{"date-parts":[[2019,12,11]]}},"container-title":["2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8974168\/8994692\/08994693.pdf?arnumber=8994693","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:09:13Z","timestamp":1657854553000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8994693\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,12]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/reconfig48160.2019.8994693","relation":{},"subject":[],"published":{"date-parts":[[2019,12]]}}}