{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T12:50:31Z","timestamp":1730292631889,"version":"3.28.0"},"reference-count":63,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,12]]},"DOI":"10.1109\/reconfig48160.2019.8994777","type":"proceedings-article","created":{"date-parts":[[2020,2,14]],"date-time":"2020-02-14T03:23:28Z","timestamp":1581650608000},"page":"1-8","source":"Crossref","is-referenced-by-count":2,"title":["Approximate Adder Tree Synthesis for FPGAs"],"prefix":"10.1109","author":[{"given":"Sina","family":"Boroumand","sequence":"first","affiliation":[]},{"given":"Philip","family":"Brisk","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2009.50"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.881557"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1964.263830"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046195"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2016.12.012"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2015.17"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/12.841125"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2013.27"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/12.660163"},{"key":"ref34","first-page":"349","article-title":"Some schemes for parallel multipliers","volume":"34","author":"dadda","year":"1965","journal-title":"Alta Frequenza"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2033536"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577305"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2003.1231908"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858314"},{"key":"ref28","first-page":"171","article-title":"Efficient high speed compression trees on xilinx fpgas","author":"kumm","year":"2014","journal-title":"MBMV 2014 - Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2014.6868629"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927468"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2893356"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2013.6569370"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484851"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993639"},{"key":"ref21","first-page":"242","author":"parandeh-afshar","year":"2009","journal-title":"19th International Conference on Field Programmable Logic and Applications FPL 2009 August 31 - September 2 2009"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2068716.2068725"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E94.A.2579"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E96.A.2553"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.48"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1988.663601"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.1991.145532"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.146"},{"key":"ref58","article-title":"A low-power, high-performance approximate multiplier with configurable partial error recovery","author":"liu","year":"2014","journal-title":"Proceedings of the Conference on Design Automation & Test in Europe European Design and Automation Association"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342073"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1007\/BF00929625"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2008.01.005"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1023\/A:1015333103608"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/92.386228"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/4.84935"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2308214"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2643639"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2010.59"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7926950"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062306"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897982"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967005"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2017.8244438"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2018.8297390"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2003280"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2008.4483927"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056066"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICRC.2016.7738674"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CASES.2015.7324540"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2015.108"},{"key":"ref8","first-page":"1279","article-title":"Grater: An Approximation Workflow for Exploiting Data-Level Parallelism in FPGA Acceleration","author":"atieh lotfi","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2589750"},{"key":"ref49","first-page":"3811","article-title":"4:2 carry-save adder module","volume":"23","author":"weinberger","year":"1981","journal-title":"IBM Technical Disclosure Bulletin"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2015.7315159"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358052"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1007\/BF02409399"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675870"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1977.1674730"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/92.238424"},{"key":"ref41","first-page":"1021","article-title":"Parallel counters","volume":"22","author":"s","year":"1973","journal-title":"IEEE Trans Computers"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364632"},{"key":"ref43","doi-asserted-by":"crossref","first-page":"1487","DOI":"10.1109\/TCAD.2003.818301","article-title":"Synthesis of arithmetic circuits considering layout effects","volume":"22","author":"um","year":"2003","journal-title":"IEEE Trans on CAD of Integrated Circuits and Systems"}],"event":{"name":"2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","start":{"date-parts":[[2019,12,9]]},"location":"Cancun, Mexico","end":{"date-parts":[[2019,12,11]]}},"container-title":["2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8974168\/8994692\/08994777.pdf?arnumber=8994777","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,14]],"date-time":"2022-07-14T23:09:12Z","timestamp":1657840152000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8994777\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,12]]},"references-count":63,"URL":"https:\/\/doi.org\/10.1109\/reconfig48160.2019.8994777","relation":{},"subject":[],"published":{"date-parts":[[2019,12]]}}}