{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,11]],"date-time":"2025-09-11T18:44:23Z","timestamp":1757616263539,"version":"3.44.0"},"reference-count":8,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,12]]},"DOI":"10.1109\/reconfig48160.2019.8994801","type":"proceedings-article","created":{"date-parts":[[2020,2,14]],"date-time":"2020-02-14T03:23:28Z","timestamp":1581650608000},"page":"1-2","source":"Crossref","is-referenced-by-count":0,"title":["Efficient FPGA Cost-Performance Space Exploration using Type-Driven Program Transformations"],"prefix":"10.1109","author":[{"given":"Cristian","family":"Urlea","sequence":"first","affiliation":[{"name":"School of Computing Science, University of Glasgow,Glasgow,United Kingdom"}]},{"given":"Wim","family":"Vanderbauwhede","sequence":"additional","affiliation":[{"name":"School of Computing Science, University of Glasgow,Glasgow,United Kingdom"}]},{"given":"Syed Waqar","family":"Nabi","sequence":"additional","affiliation":[{"name":"School of Computing Science, University of Glasgow,Glasgow,United Kingdom"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1002\/asl.377"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339272"},{"key":"ref6","first-page":"30","article-title":"Vivado design suite","volume":"5","author":"feist","year":"2012","journal-title":"White Paper"},{"key":"ref5","first-page":"200","author":"k\u00e4mpf","year":"0","journal-title":"Ocean Modelling for Beginners Using Open-source Software"},{"key":"ref8","article-title":"Intel HLS Compiler: Fast Design, Coding, and Hardware","author":"sussmann","year":"2017","journal-title":"White Paper"},{"key":"ref7","article-title":"FPGA design space exploration for scientific HPC applications using a fast and accurate cost model based on roofline analysis","author":"nabi","year":"2017","journal-title":"Journal of Parallel and Distributed Computing"},{"journal-title":"The OpenCL Specification","year":"2009","key":"ref2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-018-0572-z"}],"event":{"name":"2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","start":{"date-parts":[[2019,12,9]]},"location":"Cancun, Mexico","end":{"date-parts":[[2019,12,11]]}},"container-title":["2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8974168\/8994692\/08994801.pdf?arnumber=8994801","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,5]],"date-time":"2025-09-05T18:14:25Z","timestamp":1757096065000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8994801\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,12]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/reconfig48160.2019.8994801","relation":{},"subject":[],"published":{"date-parts":[[2019,12]]}}}