{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T15:33:15Z","timestamp":1729611195882,"version":"3.28.0"},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,6]]},"DOI":"10.1109\/recosoc.2011.5981496","type":"proceedings-article","created":{"date-parts":[[2011,9,12]],"date-time":"2011-09-12T18:03:34Z","timestamp":1315850614000},"page":"1-8","source":"Crossref","is-referenced-by-count":0,"title":["Fast prototyping environment for embedded reconfigurable units"],"prefix":"10.1109","author":[{"given":"Damien","family":"Picard","sequence":"first","affiliation":[]},{"given":"Loic","family":"Lagadec","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045071"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008807631619"},{"key":"ref12","first-page":"503","article-title":"Describing instruction set processors using nml","author":"fauth","year":"1995","journal-title":"Proc of the European Design and Test Conference (EDTC)"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"933","DOI":"10.1109\/DAC.1999.782231","article-title":"Lisa-machine description language for cycle-accurate models of programmable dsp architectures","author":"pees","year":"1999","journal-title":"Proc Design Automation Conf (DAC 99)"},{"journal-title":"System Level Design","year":"0","key":"ref14"},{"key":"ref15","first-page":"164","article-title":"Automatic transistor and physical design of fpga tiles from an architectural specifi-cation","author":"padalia","year":"2003","journal-title":"Proc Int Symp Field Programmable Gate Arrays (FPGA)"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"213","DOI":"10.1007\/3-540-63465-7_226","article-title":"Vpr: A new packing, placement and routing tool for fpga research","author":"betz","year":"1997","journal-title":"International Conference on Field Programmable Logic and Applications (FPL)"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"61","DOI":"10.1007\/978-3-540-45234-8_7","article-title":"Adres: An architecture with tightly coupled vliw processor and coarse-grained reconfigurable matrix","volume":"2778","author":"mei","year":"2003","journal-title":"Field-Programmable Logic and Applications"},{"journal-title":"Language-driven Exploration and Implementation of Partially Re-configurable ASIPs","year":"2008","author":"chattopadhyay","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2009.151"},{"journal-title":"Target Compiler Technologies","year":"0","author":"company","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1231200"},{"key":"ref6","first-page":"40","article-title":"Component selection and matching for ip-based design","author":"martin","year":"2001","journal-title":"Proc of Conference on Design Automation and Test in Europe (DATE'01)"},{"journal-title":"Xupv5–1×110t","year":"0","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/972627.972633"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1142980.1142985"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2004.1260725"},{"key":"ref1","first-page":"56","article-title":"Cramming more components onto integrated circuits","author":"moore","year":"2000","journal-title":"Readings in Computer Architecture"},{"key":"ref9","first-page":"109","article-title":"Architecture description languages for systems-on-chip design","author":"tomiyama","year":"1999","journal-title":"Proc Asia Pacific Conf Chip Design Language"},{"key":"ref20","first-page":"69","article-title":"Object-oriented meta tools for reconfigurable architectures","volume":"4693","author":"lagadec","year":"2002","journal-title":"Proc of the Modeling Signal Processing and Control Conference"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/2.839324"},{"key":"ref21","first-page":"21","article-title":"A pipelined configurable gate array for embedded processors","author":"lodi","year":"2003","journal-title":"Proc Int Symp Field Programmable Gate Arrays (FPGA)"},{"journal-title":"Tech Rep","article-title":"Connecting customized ip to the microblaze soft processor using the fast simplex link (fsl) channel","year":"2004","key":"ref24"},{"journal-title":"MicroBlaze Soft Processor","year":"0","key":"ref23"}],"event":{"name":"2011 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","start":{"date-parts":[[2011,6,20]]},"location":"Montpellier, France","end":{"date-parts":[[2011,6,22]]}},"container-title":["6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5967008\/5981488\/05981496.pdf?arnumber=5981496","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,6,23]],"date-time":"2020-06-23T18:07:24Z","timestamp":1592935644000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5981496\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/recosoc.2011.5981496","relation":{},"subject":[],"published":{"date-parts":[[2011,6]]}}}