{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:06:37Z","timestamp":1759147597205,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,6]]},"DOI":"10.1109\/recosoc.2011.5981513","type":"proceedings-article","created":{"date-parts":[[2011,9,12]],"date-time":"2011-09-12T14:03:34Z","timestamp":1315836214000},"page":"1-9","source":"Crossref","is-referenced-by-count":6,"title":["A self-reconfigurable platform for general purpose image processing systems on low-cost spartan-6 FPGAs"],"prefix":"10.1109","author":[{"given":"Salih","family":"Bayar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arda","family":"Yurdakul","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mehmet","family":"Tukel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"emphCNN based Hole filler template design using numerical integration techniques","author":"murugesan","year":"2007","journal-title":"ICANN'07 Proceedings of the 17th international conference on Artificial neural networks"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/81.661683"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2010.5681426"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"365","DOI":"10.17485\/ijst\/2010\/v3i4.1","article-title":"Internal dynamic partial reconfiguration for real time signal processing on FPGA","volume":"3","author":"bhandari","year":"2010","journal-title":"Indian Journal of Science and Technology"},{"key":"ref14","article-title":"Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs","author":"h\u00fcbner","year":"2010","journal-title":"IPDPSW'10"},{"key":"ref15","article-title":"FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA","author":"duhem","year":"2011","journal-title":"ARC 2011"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272463"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2010.5470800"},{"key":"ref18","article-title":"High-Level Design for FPGA-based Multiprocessor Accelerators","author":"g\u00f6hringer","year":"2011","journal-title":"Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing (DATE‘2011)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/854241"},{"key":"ref4","article-title":"Energy reduction by systematic run-time reconfigurable hardware deactivation","volume":"4","author":"osborne","year":"2009","journal-title":"Transactions on HiPEAC"},{"key":"ref3","article-title":"Energy Reduction with Run-Time Partial Reconfiguration","author":"liu","year":"2009","journal-title":"Technical Report of Microsoft Research MSR-TR-2009–2017"},{"key":"ref6","article-title":"An efficient self-reconfiguration core for run-time reconfigurable fpga interconnects","author":"bayar","year":"2011","journal-title":"journal of Systems Architecture JSA' 2011"},{"key":"ref5","first-page":"751","article-title":"emphPower Consumption Reduction Through Dynamic Reconfiguration","author":"lorenz","year":"2004","journal-title":"Proceedings of FPL"},{"article-title":"Cellular Neural Networs and Visual Computing","year":"2002","author":"chua","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/82.222815"},{"key":"ref2","article-title":"Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems","author":"paulsson","year":"2007","journal-title":"ReCoSoC"},{"key":"ref9","first-page":"261","article-title":"CNN Image Processing on a Xilinx Virtex-II 6000","volume":"3","author":"malki","year":"2003","journal-title":"Proc ECCTD'03"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/RME.2008.4595744"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"236","DOI":"10.1117\/12.420917","article-title":"CNN computer for high-speed visual inspection","author":"montufar-chaveznava","year":"2001","journal-title":"Proceedings SPIE"},{"journal-title":"Company Release","article-title":"The low-cost Spartan-6 FPGA family delivers an optimal balance of low risk, low cost, low power, and high performance","year":"2009","key":"ref22"},{"key":"ref21","article-title":"Xilinx launches Spartan-6, Virtex-6 FPGAs","author":"clarke","year":"2009","journal-title":"EETimes"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/CNNA.2010.5430316"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/31.7600"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1002\/cta.507"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/CNNA.2008.4588644"}],"event":{"name":"2011 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","start":{"date-parts":[[2011,6,20]]},"location":"Montpellier, France","end":{"date-parts":[[2011,6,22]]}},"container-title":["6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5967008\/5981488\/05981513.pdf?arnumber=5981513","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,4]],"date-time":"2021-12-04T07:57:57Z","timestamp":1638604677000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5981513\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/recosoc.2011.5981513","relation":{},"subject":[],"published":{"date-parts":[[2011,6]]}}}