{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,11]],"date-time":"2025-09-11T17:16:03Z","timestamp":1757610963904,"version":"3.44.0"},"reference-count":23,"publisher":"IEEE","license":[{"start":{"date-parts":[[2011,6,1]],"date-time":"2011-06-01T00:00:00Z","timestamp":1306886400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2011,6,1]],"date-time":"2011-06-01T00:00:00Z","timestamp":1306886400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,6]]},"DOI":"10.1109\/recosoc.2011.5981516","type":"proceedings-article","created":{"date-parts":[[2011,9,12]],"date-time":"2011-09-12T14:03:34Z","timestamp":1315836214000},"page":"1-8","source":"Crossref","is-referenced-by-count":0,"title":["An approach for power and performance evaluation of reconfigurable SoC at mixed abstraction levels"],"prefix":"10.1109","author":[{"given":"Matthias","family":"Kuehnle","sequence":"first","affiliation":[{"name":"Institute of Information Processing Technology Karlsruhe Institute of Technology, Karlsruhe, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alisson","family":"Brito","sequence":"additional","affiliation":[{"name":"Departamento de Ciencias Exatas Universidade Federal da Paraiba, Joao Pessoa, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christoph","family":"Roth","sequence":"additional","affiliation":[{"name":"Institute of Information Processing Technology Karlsruhe Institute of Technology, Karlsruhe, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matthias","family":"Kruesselin","sequence":"additional","affiliation":[{"name":"Institute of Information Processing Technology Karlsruhe Institute of Technology, Karlsruhe, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Juergen","family":"Becker","sequence":"additional","affiliation":[{"name":"Institute of Information Processing Technology Karlsruhe Institute of Technology, Karlsruhe, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISABEL.2008.4712587"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796538"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.27"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253814"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2006.1639448"},{"key":"ref15","article-title":"Mod-elling Tile-Based Run-Time Reconfigurable Systems Using SystemC","volume":"4","author":"albrecht","year":"2007","journal-title":"Simulation"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090805"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2003.1267734"},{"key":"ref18","article-title":"A Methodology for Modelling and Simulation of Dynamic and Partially Reconfigurable Systems","author":"brito","year":"2010","journal-title":"Alisson Vasconcelos Brito (Org) Dynamic Modelling"},{"journal-title":"V2SC - VHDL to SystemC Converter","year":"2001","author":"t\u00fcbingen","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378591"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419681"},{"key":"ref6","article-title":"SystemC for Embedded System Design","author":"lang","year":"2006","journal-title":"Seminar"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.886411"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CODESS.2004.240910"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2008.17"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"105","DOI":"10.1007\/s10617-006-9586-7","article-title":"Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems","volume":"10","author":"dhanwada","year":"2006","journal-title":"Design Automation for Embedded Systems"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1084834.1084874"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.998629"},{"key":"ref20","article-title":"A Mixed-Signal System-on-Chip Audio Decoder Design for Education","author":"k\u00f6nig","year":"2007","journal-title":"RC Education 2007"},{"journal-title":"AMBA Specification Rev2 0","year":"1999","key":"ref22"},{"journal-title":"Leon3 Processor","year":"2011","author":"gaisler","key":"ref21"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2004.8"}],"event":{"name":"2011 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","start":{"date-parts":[[2011,6,20]]},"location":"Montpellier, France","end":{"date-parts":[[2011,6,22]]}},"container-title":["6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5967008\/5981488\/05981516.pdf?arnumber=5981516","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,3]],"date-time":"2025-09-03T17:50:55Z","timestamp":1756921855000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5981516\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/recosoc.2011.5981516","relation":{},"subject":[],"published":{"date-parts":[[2011,6]]}}}