{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:53:42Z","timestamp":1729630422492,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,6]]},"DOI":"10.1109\/recosoc.2011.5981530","type":"proceedings-article","created":{"date-parts":[[2011,9,12]],"date-time":"2011-09-12T18:03:34Z","timestamp":1315850614000},"page":"1-5","source":"Crossref","is-referenced-by-count":5,"title":["Simulations of NoC topologies for generalized hierarchical completely-connected networks"],"prefix":"10.1109","author":[{"given":"Toshinori","family":"Takabatake","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/s11235-008-9077-1"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICET.2006.335967"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1465352"},{"key":"ref13","first-page":"1292","article-title":"On chip network: topology design and evaluation using NS2","volume":"2","author":"ngo","year":"2005","journal-title":"The 7th Int'l Conf Advanced Communication Technology 2005 (ICACT 2005)"},{"key":"ref14","article-title":"Simulation and Evaluation for a Network on Chip Architecture Using Ns-2","author":"sun","year":"2002","journal-title":"Proc IEEE Norchip Conf"},{"key":"ref15","first-page":"1216","article-title":"HCC: Generalized hierarchical completely-connected networks","volume":"e83 d","author":"takabatake","year":"2000","journal-title":"IEICE Trans Information & Systems"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1142\/S0219265908002199"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1016\/0167-739X(88)90007-6"},{"journal-title":"Ns-2 Network Simulator","year":"2011","key":"ref18"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2061613"},{"journal-title":"Networks on Chips Technology and Tools","year":"2006","author":"de micheli","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2002.1016885"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2010691"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2005.37"},{"key":"ref7","article-title":"Spidergon: A novel on-chip communication net-work","author":"coppola","year":"2004","journal-title":"Proc Int'l Symp System-on-Chip"},{"key":"ref2","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-3387-7","author":"xu","year":"2001","journal-title":"Topological Structure and Analysis of Interconnection Networks"},{"journal-title":"Parallel System Interconnections and Communications","year":"2001","author":"grammatikakis","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243841"}],"event":{"name":"2011 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","start":{"date-parts":[[2011,6,20]]},"location":"Montpellier, France","end":{"date-parts":[[2011,6,22]]}},"container-title":["6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5967008\/5981488\/05981530.pdf?arnumber=5981530","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T06:11:42Z","timestamp":1497939102000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5981530\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/recosoc.2011.5981530","relation":{},"subject":[],"published":{"date-parts":[[2011,6]]}}}