{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,15]],"date-time":"2026-01-15T14:36:40Z","timestamp":1768487800480,"version":"3.49.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,6]]},"DOI":"10.1109\/recosoc.2011.5981545","type":"proceedings-article","created":{"date-parts":[[2011,9,12]],"date-time":"2011-09-12T14:03:34Z","timestamp":1315836214000},"page":"1-8","source":"Crossref","is-referenced-by-count":57,"title":["The Xilinx Design Language (XDL): Tutorial and use cases"],"prefix":"10.1109","author":[{"given":"Christian","family":"Beckhoff","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dirk","family":"Koch","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jim","family":"Torresen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"A Standalone Wire Database for Routing and Tracing in Xilinx Virtex, Virtex-E, and Virtex-II FPGAs","author":"steiner","year":"2002"},{"key":"ref11","article-title":"Partial Reconfiguration User Guide","year":"2009"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311188"},{"key":"ref13","year":"2002","journal-title":"Two flows for partial reconfiguration module based or difference based"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508170"},{"key":"ref15","year":"2010","journal-title":"PlanAhead Design Analysis Tool"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.36"},{"key":"ref3","article-title":"An XDL-Based Busmacro Generator for Customizable Communication Interfaces for Dynamically and Partially Reconfigurable Systems","author":"claus","year":"2007","journal-title":"Workshop on Reconfigurable Computing Education at ISVLSI 2007"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950425"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2010.5681429"},{"key":"ref8","year":"2000","journal-title":"Xilinx Design Language"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-00641-8_9"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.144"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2008.4629918"},{"key":"ref9","article-title":"The Hoplite Guide To Run-Time Reconfigurable-Computing","author":"scarpino","year":"2008"}],"event":{"name":"2011 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","location":"Montpellier, France","start":{"date-parts":[[2011,6,20]]},"end":{"date-parts":[[2011,6,22]]}},"container-title":["6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5967008\/5981488\/05981545.pdf?arnumber=5981545","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T06:39:23Z","timestamp":1490078363000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5981545\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/recosoc.2011.5981545","relation":{},"subject":[],"published":{"date-parts":[[2011,6]]}}}