{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T12:51:36Z","timestamp":1730292696811,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,7]]},"DOI":"10.1109\/retis.2015.7232927","type":"proceedings-article","created":{"date-parts":[[2015,9,3]],"date-time":"2015-09-03T21:42:07Z","timestamp":1441316527000},"page":"481-484","source":"Crossref","is-referenced-by-count":1,"title":["Implementation of 4-bit carry select adder using Diode free adiabatic logic (DFAL)"],"prefix":"10.1109","author":[{"given":"Sanjay","family":"Singh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Srinivasarao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","article-title":"RKNagari, and SPSingh, Diodefree","volume":"2013","author":"shipraupadhay","year":"0","journal-title":"Adiabatic logic circuits hindawani published corporations ISRN Electronics"},{"journal-title":"EnergyEfficient Adiabatic Logic for Low Power VLSI Applications 2011 International Conference on Communication Systems and Network Technologies","year":"2011","author":"maury","key":"ref3"},{"article-title":"design and analysis of mux using Adiabatic techniquesECRL AND PFAL","year":"2013","author":"kumar","key":"ref10"},{"journal-title":"kittur low-power and area-efficient carry select adder ieee transactions on very large scale integration (vlsi) systems","year":"0","author":"ramkumar","key":"ref6"},{"journal-title":"Fundamental Logics Based On Two Phase Clocked Adiabatic Static CMOS Logic 978&#x2013;1-4244-5091-6\/09\/$25 00&#x00A9;2009IEEE","year":"0","author":"anua","key":"ref11"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IRETELC.1962.5407919"},{"journal-title":"Principle of CMOS VLSI Design System Prospective 2nd","year":"1993","author":"waste","key":"ref8"},{"key":"ref7","volume":"3","author":"kumar","year":"2012","journal-title":"Study of Various Full Adders using Tanner EDA Tool IJCST"},{"journal-title":"sharatc prasad copy right 2000","article-title":"Low power cmos VLSI circuit design Kaushik Roy","year":"0","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICETET.2008.47"},{"article-title":"Low Power Digital Design","year":"1995","author":"chandrakasan","key":"ref1"}],"event":{"name":"2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS)","start":{"date-parts":[[2015,7,9]]},"location":"Kolkata, India","end":{"date-parts":[[2015,7,11]]}},"container-title":["2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7185253\/7232836\/07232927.pdf?arnumber=7232927","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,25]],"date-time":"2017-03-25T04:46:06Z","timestamp":1490417166000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7232927\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/retis.2015.7232927","relation":{},"subject":[],"published":{"date-parts":[[2015,7]]}}}