{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T04:57:27Z","timestamp":1760245047983,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1109\/rivf.2019.8713613","type":"proceedings-article","created":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T21:27:30Z","timestamp":1558042050000},"page":"1-6","source":"Crossref","is-referenced-by-count":3,"title":["A Scalable Network-on-Chip Based Neural Network Implementation on FPGAs"],"prefix":"10.1109","author":[{"given":"Thanh Thi","family":"Thanh Bui","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Braden","family":"Phillips","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHP.2012.6403122"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.23"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CODES-ISSS.2013.6659006"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/12.956089"},{"journal-title":"The MNIST Database of Handwritten Digits","year":"2017","author":"lecun","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.5573\/JSTS.2010.10.1.028"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2011.2133210"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2011.2158843"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2007.891626"},{"key":"ref5","first-page":"703","author":"suaste-rivas","year":"2006","journal-title":"Hybrid Neural Network Design and Implementation on FPGA for Infant Cry Recognition"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2015.2413754"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2007.911946"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"239","DOI":"10.1016\/j.neucom.2010.03.021","article-title":"Artificial Neural Networks in Hardware: A Survey of Two Decades of Progress","volume":"74","author":"misra","year":"2010","journal-title":"Neurocomputing"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-7012(00)00201-3"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2004.1362404"}],"event":{"name":"2019 IEEE-RIVF International Conference on Computing and Communication Technologies (RIVF)","start":{"date-parts":[[2019,3,20]]},"location":"Danang, Vietnam","end":{"date-parts":[[2019,3,22]]}},"container-title":["2019 IEEE-RIVF International Conference on Computing and Communication Technologies (RIVF)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8705149\/8713612\/08713613.pdf?arnumber=8713613","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,19]],"date-time":"2022-07-19T20:18:41Z","timestamp":1658261921000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8713613\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/rivf.2019.8713613","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}