{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T13:05:52Z","timestamp":1730293552683,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,9,24]],"date-time":"2020-09-24T00:00:00Z","timestamp":1600905600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,9,24]],"date-time":"2020-09-24T00:00:00Z","timestamp":1600905600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,9,24]],"date-time":"2020-09-24T00:00:00Z","timestamp":1600905600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,9,24]]},"DOI":"10.1109\/rsp51120.2020.9244856","type":"proceedings-article","created":{"date-parts":[[2020,11,4]],"date-time":"2020-11-04T21:13:22Z","timestamp":1604524402000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["Mathematic models based on multiple-criteria decision analysis for tuning industrial CNN in an FPGA computing cluster"],"prefix":"10.1109","author":[{"given":"Chen","family":"WU","sequence":"first","affiliation":[]},{"given":"Virginie","family":"FRESSE","sequence":"additional","affiliation":[]},{"given":"Benoit","family":"SUFFRAN","sequence":"additional","affiliation":[]},{"given":"Hubert","family":"KONIK","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Scalable and modularized rtl compilation of convolutional neural networks onto fpga","author":"ma","year":"2016","journal-title":"Int Conference on Field Programmable Logic and Applications"},{"key":"ref11","first-page":"1","article-title":"A high performance fpga-based accelerator for large-scale convolutional neural networks","author":"li","year":"2016","journal-title":"Int Conference on Field Programmable Logic and Applications"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1145\/2749469.2750389"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/FCCM.2017.25"},{"key":"ref14","article-title":"Deep learning with int8 optimization on xilinx devices","author":"fu","year":"2016","journal-title":"White Paper"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/ACCESS.2018.2890150"},{"key":"ref16","article-title":"Optimizing loop operation and dataflow in fpga acceleration of deep cnn","author":"ma","year":"2017","journal-title":"International Symposium on Field-Programmable Gate Arrays"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/FCCM.2016.22"},{"key":"ref18","article-title":"Hardware automated dataflow deployment of cnns","volume":"abs 1705 4543","author":"abdelouahab","year":"2017","journal-title":"CoRR"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1145\/3020078.3021741"},{"key":"ref4","article-title":"Angel-eye: A complete design flow for mapping cnn onto embedded fpga","author":"guo","year":"2017","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1145\/2847263.2847265"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.3390\/electronics8030295"},{"key":"ref5","article-title":"Optimizing fpga-based accelerator design for deep convolutional neural networks","author":"zhang","year":"2015","journal-title":"Proceedings of the ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"},{"key":"ref8","article-title":"FINN: A framework for fast, scalable binarized neural network inference","volume":"abs 1612 7119","author":"umuroglu","year":"2016","journal-title":"CoRR"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/TCAD.2017.2785257"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1145\/3061639.3062244"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1007\/978-3-642-01970-8_92"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1016\/j.vlsi.2017.12.009"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1016\/j.neucom.2017.09.046"}],"event":{"name":"2020 IEEE International Workshop on Rapid System Prototyping (RSP)","start":{"date-parts":[[2020,9,24]]},"location":"Hamburg, Germany","end":{"date-parts":[[2020,9,25]]}},"container-title":["2020 International Workshop on Rapid System Prototyping (RSP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9244848\/9244849\/09244856.pdf?arnumber=9244856","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,28]],"date-time":"2022-06-28T21:53:49Z","timestamp":1656453229000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9244856\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,24]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/rsp51120.2020.9244856","relation":{},"subject":[],"published":{"date-parts":[[2020,9,24]]}}}