{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T02:19:52Z","timestamp":1729649992851,"version":"3.28.0"},"reference-count":30,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,10,14]],"date-time":"2021-10-14T00:00:00Z","timestamp":1634169600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,10,14]],"date-time":"2021-10-14T00:00:00Z","timestamp":1634169600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,10,14]]},"DOI":"10.1109\/rsp53691.2021.9806205","type":"proceedings-article","created":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T20:57:00Z","timestamp":1656363420000},"page":"57-63","source":"Crossref","is-referenced-by-count":1,"title":["Heterogeneous Logic Implementation for Adders in VTR"],"prefix":"10.1109","author":[{"given":"Harpreet","family":"Kaur","sequence":"first","affiliation":[{"name":"University of New Brunswick,Faculty of Computer Science,Fredericton,Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Georgiy","family":"Krylov","sequence":"additional","affiliation":[{"name":"University of New Brunswick,Faculty of Computer Science,Fredericton,Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seyed Alireza","family":"Damghani","sequence":"additional","affiliation":[{"name":"University of New Brunswick,Faculty of Computer Science,Fredericton,Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kenneth B.","family":"Kent","sequence":"additional","affiliation":[{"name":"University of New Brunswick,Faculty of Computer Science,Fredericton,Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"article-title":"Collecting and analyzing netlist statistics in odin-ii","year":"2019","author":"flawn","key":"ref30"},{"journal-title":"Field-Programmable Gate Array Technology","year":"2012","author":"trimberger","key":"ref10"},{"key":"ref11","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4614-3594-5","author":"farooq","year":"2012","journal-title":"Tree-Based Heterogeneous FPGA Architectures Application Specific Exploration and Optimization"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/0-387-26104-4_3"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2013.6683953"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"68","DOI":"10.1049\/ecej:19970203","article-title":"verilog: accelerating digital design","volume":"9","author":"blair","year":"1997","journal-title":"Electronics & Communication Engineering Journal"},{"key":"ref15","volume":"17837","author":"hyde","year":"1995","journal-title":"CSCI 320 Computer Architecture Handbook on Verilog HDL"},{"journal-title":"IEEE Standard Verilog Hardware Description Language (IEEE Std 1364-2001)","year":"2006","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2013.6683953"},{"journal-title":"Verilog-to-routing documentation","year":"2016","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145708"},{"year":"2021","key":"ref28","article-title":"Flagship heterogeneous architecture with carry chains for vtr 7.0"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1989.56691"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/RSP51120.2020.9244862"},{"key":"ref3","first-page":"277","article-title":"Configurable hardware: A new paradigm for computation","author":"gray","year":"1989","journal-title":"Decennial Caltech Conference on VLSI"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2004.1319911"},{"year":"2021","key":"ref29","article-title":"Architecture with no fracturable luts"},{"journal-title":"Master’s thesis","year":"2013","author":"wang","key":"ref5"},{"journal-title":"Master’s thesis","year":"2014","author":"yan","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2014.25"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.62145"},{"key":"ref9","volume":"497","author":"betz","year":"2012","journal-title":"Architecture and CAD for Deep-Submicron FPGAs"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD51259.2020.00018"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2005.1515739"},{"journal-title":"Ph D Dissertation","year":"2018","author":"gharibian","key":"ref22"},{"year":"2016","key":"ref21","article-title":"Verilog to routing–open source cad flow for fpga research"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2012.10.003"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.31"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3388617"},{"key":"ref25","first-page":"62","article-title":"Comparison between various types of adder topologies","volume":"6","author":"kaur","year":"2015","journal-title":"IJCST"}],"event":{"name":"2021 IEEE International Workshop on Rapid System Prototyping (RSP)","start":{"date-parts":[[2021,10,14]]},"location":"Paris, France","end":{"date-parts":[[2021,10,14]]}},"container-title":["2021 IEEE International Workshop on Rapid System Prototyping (RSP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9806044\/9806146\/09806205.pdf?arnumber=9806205","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,2,9]],"date-time":"2023-02-09T20:20:42Z","timestamp":1675974042000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9806205\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10,14]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/rsp53691.2021.9806205","relation":{},"subject":[],"published":{"date-parts":[[2021,10,14]]}}}