{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T10:08:21Z","timestamp":1767262101296,"version":"3.28.0"},"reference-count":37,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,4]]},"DOI":"10.1109\/rtas.2014.6925994","type":"proceedings-article","created":{"date-parts":[[2015,1,21]],"date-time":"2015-01-21T14:35:37Z","timestamp":1421850937000},"page":"101-110","source":"Crossref","is-referenced-by-count":85,"title":["FlexPRET: A processor platform for mixed-criticality systems"],"prefix":"10.1109","author":[{"given":"Michael","family":"Zimmer","sequence":"first","affiliation":[]},{"given":"David","family":"Broman","sequence":"additional","affiliation":[]},{"given":"Chris","family":"Shaver","sequence":"additional","affiliation":[]},{"given":"Edward A.","family":"Lee","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"JOP A Java Optimized Processor for Embedded Real-Time Systems","year":"2008","author":"schoeberl","key":"ref33"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/EMRTS.2003.1212740"},{"key":"ref31","first-page":"264","article-title":"The case for the precision timed (PRET) machine","author":"edwards","year":"2007","journal-title":"Proceedings ACM\/IEEE Design Automation Conference (DAC)"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2003.814618"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2014.6925993"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/DASC.2008.4702770"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.78"},{"key":"ref34","article-title":"Predictable platforms for safety-critical embedded systems","author":"andalam","year":"2013","journal-title":"Thesis The University of Auckland"},{"key":"ref10","article-title":"Mixed criticality systems: A review","author":"burns","year":"2013","journal-title":"Department of Computer Science University of York Tech Rep MCC-1(b)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2012.24"},{"journal-title":"Design of a Computer The Control Data 6600","year":"1970","author":"thornton","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.35"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378622"},{"journal-title":"The XMOS XS1 Architecture XMOS","year":"2009","author":"may","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1347375.1347389"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1450095.1450117"},{"article-title":"Precision timed machines","year":"2012","author":"liu","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/11802167_46"},{"journal-title":"Wind River VxWorks 653 Platform","year":"0","key":"ref28"},{"journal-title":"DO178C Software Considerations in Airborne Systems and Equipment Certification","year":"2012","key":"ref4"},{"key":"ref27","first-page":"136","article-title":"The mälardalen WCET benchmarks: Past, present and future","volume":"15","author":"gustafsson","year":"2010","journal-title":"6th Intl Workshop on Worst-Case Execution Time (WCET) Analysis"},{"year":"2010","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DASC.2007.4391842"},{"key":"ref29","article-title":"Requirements for and design of a processor with predictable timing","author":"berg","year":"2004","journal-title":"Perspectives Workshop Design of Systems with Predictable Behaviour"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/5.259424"},{"key":"ref8","first-page":"291","article-title":"On the scheduling of mixed-criticality real-time task sets","author":"de niz","year":"2009","journal-title":"Proc IEEE Real-Time Systems Symposium (RTSS)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2008.26"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2010.10"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CIT.2010.320"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2007.47"},{"key":"ref20","article-title":"The RISC-V instruction set manual, volume I: Base user-level ISA","author":"waterman","year":"2011","journal-title":"EECS Department University of California Berkeley Technical Report No UCB\/IEECS-2011-18"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/774789.774805"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024787"},{"key":"ref24","article-title":"Precision timed infrastructure: Design challenges","author":"broman","year":"2013","journal-title":"Electronic System Level Synthesis Conference (ESLsyn)"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2014.6926001"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008186323068"}],"event":{"name":"2014 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","start":{"date-parts":[[2014,4,15]]},"location":"Berlin, Germany","end":{"date-parts":[[2014,4,17]]}},"container-title":["2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6917167\/6925980\/06925994.pdf?arnumber=6925994","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T21:31:32Z","timestamp":1490304692000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6925994\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,4]]},"references-count":37,"URL":"https:\/\/doi.org\/10.1109\/rtas.2014.6925994","relation":{},"subject":[],"published":{"date-parts":[[2014,4]]}}}