{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,3]],"date-time":"2025-12-03T17:41:42Z","timestamp":1764783702634},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,4]]},"DOI":"10.1109\/rtas.2014.6925996","type":"proceedings-article","created":{"date-parts":[[2015,1,21]],"date-time":"2015-01-21T19:35:37Z","timestamp":1421868937000},"page":"125-134","source":"Crossref","is-referenced-by-count":11,"title":["Precise shared cache analysis using optimal interference placement"],"prefix":"10.1109","author":[{"given":"Kartik","family":"Nagar","sequence":"first","affiliation":[]},{"given":"Y.N.","family":"Srikant","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555764"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2011.28"},{"key":"ref12","article-title":"Making shared caches more predictable on multicore platforms","author":"ward","year":"2013","journal-title":"ECRTS"},{"key":"ref13","article-title":"Cache-aware scheduling and analysis for multicores","author":"guan","year":"2012","journal-title":"EMSOFT"},{"key":"ref14","article-title":"WCET analysis of multi-level noninclusive set-associative instruction caches","author":"hardy","year":"2008","journal-title":"RTSS"},{"key":"ref15","article-title":"Efficient microarchitecture modeling and path analysis for real-time software","author":"stevenlee","year":"1995","journal-title":"RTSS"},{"key":"ref16","article-title":"Cache modeling for real-time software: Beyond direct mapped instruction caches","author":"stevenlee","year":"1996","journal-title":"RTSS"},{"journal-title":"WCET project","year":"0","key":"ref17"},{"key":"ref4","article-title":"WCET analysis for multi-core processors with shared 12 instruction caches","author":"yan","year":"2008","journal-title":"RTAS"},{"key":"ref3","first-page":"56","article-title":"Chronos: A timing analyzer for embedded software","author":"xianfeng","year":"69","journal-title":"Science of Computer Programming"},{"key":"ref6","article-title":"Timing analysis of concurrent programs running on shared cache multi-cores","author":"yan","year":"2009","journal-title":"RTSS"},{"key":"ref5","article-title":"Accurately estimating worst-case execution time for multi-core processors with shared direct-mapped instruction caches","author":"yan","year":"2009","journal-title":"RTCSA"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2011.25"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2012.26"},{"key":"ref2","article-title":"Performance analysis of embedded software using implicit path enumeration","author":"stevenlee","year":"1995","journal-title":"DAC"},{"key":"ref1","article-title":"Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches","author":"hardy","year":"2009","journal-title":"RTSS"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391545"}],"event":{"name":"2014 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","start":{"date-parts":[[2014,4,15]]},"location":"Berlin, Germany","end":{"date-parts":[[2014,4,17]]}},"container-title":["2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6917167\/6925980\/06925996.pdf?arnumber=6925996","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T01:31:19Z","timestamp":1490319079000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6925996\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,4]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/rtas.2014.6925996","relation":{},"subject":[],"published":{"date-parts":[[2014,4]]}}}