{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T16:40:47Z","timestamp":1761324047597,"version":"3.28.0"},"reference-count":40,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/rtas.2016.7461339","type":"proceedings-article","created":{"date-parts":[[2016,4,28]],"date-time":"2016-04-28T16:18:27Z","timestamp":1461860307000},"page":"1-12","source":"Crossref","is-referenced-by-count":15,"title":["Memory Servers for Multicore Systems"],"prefix":"10.1109","author":[{"given":"Rodolfo","family":"Pellizzoni","sequence":"first","affiliation":[]},{"given":"Heechul","family":"Yun","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2012.32"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2015.24"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2016.7461361"},{"key":"ref32","article-title":"Periodic resource model for compositional real-time guarantees","author":"shin","year":"2003","journal-title":"Real-time Systems Symposium (RTSS)"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2008.4492735"},{"journal-title":"Single core equivalent virtual machines for hard real-time computing on multicore processors","year":"2014","author":"sha","key":"ref30"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2014.6925999"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2500572"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2013.44"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844484"},{"key":"ref40","article-title":"MemGuard: Memory Bandwidth Reservation System for Efficient Performance Isolation in Multi-core Platforms","author":"yun","year":"2013","journal-title":"RTAS"},{"key":"ref11","article-title":"Estimation of cache related migration delays for multi-core processors with shared instruction caches","author":"hardy","year":"2009","journal-title":"RTNS"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ETFA.2015.7301431"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2014.6925986"},{"journal-title":"Intel®64 and IA-32 Architectures Software Developer Manuals","year":"2012","key":"ref14"},{"journal-title":"Memory Characterization of Workloads Using Instrumentation-driven Simulation-a Pin-based Memory Characterization of the SPEC CPU2000 and SPEC CPU2006 Benchmark Suites","year":"2007","author":"jaleel","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2014.6925998"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2014.37"},{"key":"ref18","article-title":"Response-Time Analysis for Single Core Equivalence Framework","author":"mancuso","year":"2015","journal-title":"Euromicro Conference on Real-Time Systems (ECRTS)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1054943.1054954"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2010.24"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.103"},{"key":"ref27","first-page":"22:1","article-title":"Real-time Performance Analysis of Multiprocessor Systems with Shared Memory","volume":"10","author":"schliecker","year":"2011","journal-title":"ACM Trans Embed Comput Syst"},{"key":"ref3","article-title":"Process cruise control: Throttling memory access in a soft real-time environment","author":"bellosa","year":"1997","journal-title":"Poster Symposium on Operating Systems Principles (SOSP)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168943"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2011.28"},{"journal-title":"CAST-32 Position Paper Multi-core Processors","year":"0","key":"ref5"},{"journal-title":"Freescale e500mc Core Reference Manual (Rev 3)","year":"2013","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2014.6910550"},{"key":"ref2","article-title":"Cache-related preemption and migration delays: Empirical approximation and impact on schedulability","author":"bastoni","year":"2010","journal-title":"OSPERT"},{"key":"ref9","doi-asserted-by":"crossref","DOI":"10.7873\/DATE.2013.118","article-title":"Conservative open-page policy for mixed tim-criticality memory controllers","author":"goossens","year":"2013","journal-title":"Design Automation and Test in Europe (DATE)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289877"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/EDCC.2012.27"},{"key":"ref22","first-page":"64","article-title":"Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions","volume":"12","author":"paolieri","year":"2013","journal-title":"ACM TECS"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2014.20"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2086696.2086713"},{"journal-title":"Memory Server Code Repository","year":"0","author":"pellizzoni","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039388"}],"event":{"name":"2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","start":{"date-parts":[[2016,4,11]]},"location":"Vienna, Austria","end":{"date-parts":[[2016,4,14]]}},"container-title":["2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7460013\/7461311\/07461339.pdf?arnumber=7461339","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,6]],"date-time":"2019-09-06T23:39:01Z","timestamp":1567813141000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7461339\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":40,"URL":"https:\/\/doi.org\/10.1109\/rtas.2016.7461339","relation":{},"subject":[],"published":{"date-parts":[[2016,4]]}}}