{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,17]],"date-time":"2026-06-17T05:54:38Z","timestamp":1781675678555,"version":"3.54.5"},"reference-count":52,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,5,11]],"date-time":"2026-05-11T00:00:00Z","timestamp":1778457600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,5,11]],"date-time":"2026-05-11T00:00:00Z","timestamp":1778457600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,5,11]]},"DOI":"10.1109\/rtas68450.2026.00033","type":"proceedings-article","created":{"date-parts":[[2026,6,16]],"date-time":"2026-06-16T19:42:26Z","timestamp":1781638946000},"page":"275-288","source":"Crossref","is-referenced-by-count":0,"title":["Time-Predictable Acceleration of Deep Neural Networks on FPGA SoCs with Multi-Core DPUs"],"prefix":"10.1109","author":[{"given":"Federico","family":"Aromolo","sequence":"first","affiliation":[{"name":"Scuola Superiore Sant&#x2019;Anna,Department of Excellence in Robotics &#x0026; AI,Pisa,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Niko","family":"Salamini","sequence":"additional","affiliation":[{"name":"Scuola Superiore Sant&#x2019;Anna,Department of Excellence in Robotics &#x0026; AI,Pisa,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jacopo Del","family":"Granchio","sequence":"additional","affiliation":[{"name":"Scuola Superiore Sant&#x2019;Anna,Department of Excellence in Robotics &#x0026; AI,Pisa,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alessandro","family":"Biondi","sequence":"additional","affiliation":[{"name":"Scuola Superiore Sant&#x2019;Anna,Department of Excellence in Robotics &#x0026; AI,Pisa,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mauro","family":"Marinoni","sequence":"additional","affiliation":[{"name":"Scuola Superiore Sant&#x2019;Anna,Department of Excellence in Robotics &#x0026; AI,Pisa,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Giorgio","family":"Buttazzo","sequence":"additional","affiliation":[{"name":"Scuola Superiore Sant&#x2019;Anna,Department of Excellence in Robotics &#x0026; AI,Pisa,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173191"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/s11831-022-09741-8"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS46320.2019.00042"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCPS.2018.00035"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ETFA.2017.8247615"},{"key":"ref6","first-page":"24:1","article-title":"A bandwidth reservation mechanism for AXI-based hardware accelerators on FPGAs","volume-title":"Proceedings of the 31st Euromicro Conference on Real-Time Systems (ECRTS 2019)","author":"Pagani"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3358183"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218652"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DSD57027.2022.00061"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.23919\/DATE58400.2024.10546511"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS65571.2025.00035"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS52674.2021.00047"},{"key":"ref13","article-title":"hls4ml: An open-source codesign workflow to empower scientific low-power machine learning devices","author":"Fahim","year":"2021"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021744"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-0676-1"},{"key":"ref16","first-page":"6105","article-title":"EfficientNet: Rethinking model scaling for convolutional neural networks","volume-title":"Proceedings of the 36th International Conference on Machine Learning (ICML 2019)","author":"Tan"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV.2019.00140"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.4324\/9781410605337-29"},{"key":"ref20","volume-title":"SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <0.5MB model size","author":"Iandola","year":"2016"},{"key":"ref21","article-title":"The case for FIFO real-time scheduling","volume-title":"Tech. Rep.","author":"Altmeyer","year":"2016"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-018-9303-1"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2012.2188805"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-007-9012-7"},{"key":"ref25","first-page":"225","article-title":"Preemptive priority-based scheduling: an appropriate engineering approach","volume-title":"Advances in real-time systems","author":"Burns","year":"1995"},{"key":"ref26","article-title":"AXI traffic generator v3.0 LogiCORE IP product guide","volume-title":"Product Guide PG125","year":"2026"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2011.30"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2010.9"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2011.28"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS66672.2025.00037"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1978802.1978814"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-08696-5"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4684-2001-2_9"},{"key":"ref34","volume-title":"Computers and Intractability. A Guide to the Theory of NP-Completeness","author":"Garey","year":"1979"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1016\/S0022-0000(74)80026-7"},{"key":"ref36","article-title":"Time-predictable acceleration of deep neural networks on FPGA SoCs with multi-core DPUs (artifact)","author":"Aromolo","year":"2026"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-005-0507-9"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2018.00028"},{"key":"ref39","first-page":"443","article-title":"Serving DNNs like clockwork: Performance predictability from the bottom up","volume-title":"Proceedings of the 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 2020)","author":"Gujarati"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS48715.2020.00007"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS52674.2021.00038"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2007.25"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.70763"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2016.010"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247793"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2019.00060"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2016.31"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS52030.2021.00013"},{"key":"ref49","first-page":"13:1","article-title":"Response-time analysis for self-suspending tasks under EDF scheduling","volume-title":"Proceedings of the 34th Euromicro Conference on Real-Time Systems (ECRTS 2022)","author":"Aromolo"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS66672.2025.00049"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2018.00026"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2013.12"}],"event":{"name":"2026 IEEE 32nd Real-Time and Embedded Technology and Applications Symposium (RTAS)","location":"Saint Malo, France","start":{"date-parts":[[2026,5,11]]},"end":{"date-parts":[[2026,5,14]]}},"container-title":["2026 IEEE 32nd Real-Time and Embedded Technology and Applications Symposium (RTAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11558268\/11558364\/11558371.pdf?arnumber=11558371","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,17]],"date-time":"2026-06-17T05:22:03Z","timestamp":1781673723000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11558371\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,5,11]]},"references-count":52,"URL":"https:\/\/doi.org\/10.1109\/rtas68450.2026.00033","relation":{},"subject":[],"published":{"date-parts":[[2026,5,11]]}}}