{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T18:52:20Z","timestamp":1725475940449},"reference-count":32,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,8]]},"DOI":"10.1109\/rtcsa.2014.6910521","type":"proceedings-article","created":{"date-parts":[[2014,9,30]],"date-time":"2014-09-30T20:39:52Z","timestamp":1412109592000},"page":"1-10","source":"Crossref","is-referenced-by-count":0,"title":["PUMA: Pseudo unified memory architecture for single-ISA heterogeneous multi-core systems"],"prefix":"10.1109","author":[{"family":"Gangyong Jia","sequence":"first","affiliation":[]},{"family":"Liang Shi","sequence":"additional","affiliation":[]},{"family":"Jian Wan","sequence":"additional","affiliation":[]},{"family":"Youwei Yuan","sequence":"additional","affiliation":[]},{"family":"Xi Li","sequence":"additional","affiliation":[]},{"family":"Dong Dai","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"2001","author":"davis","journal-title":"Modern Dram Architectures","key":"19"},{"doi-asserted-by":"publisher","key":"17","DOI":"10.1145\/1950365.1950392"},{"doi-asserted-by":"publisher","key":"18","DOI":"10.1109\/12.966491"},{"doi-asserted-by":"publisher","key":"15","DOI":"10.1145\/2155620.2155624"},{"doi-asserted-by":"publisher","key":"16","DOI":"10.1145\/1736020.1736058"},{"doi-asserted-by":"publisher","key":"13","DOI":"10.1109\/HPCA.2012.6168944"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1145\/2155620.2155664"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/ISCA.2008.7"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/MICRO.2006.24"},{"key":"21","article-title":"Managing distributed, shared L2 Caches through OS-level page allocation","author":"cho","year":"2006","journal-title":"MICRO-39"},{"doi-asserted-by":"publisher","key":"20","DOI":"10.1109\/40.641593"},{"doi-asserted-by":"publisher","key":"22","DOI":"10.1145\/1735970.1736036"},{"doi-asserted-by":"publisher","key":"23","DOI":"10.1145\/1594233.1594292"},{"doi-asserted-by":"publisher","key":"24","DOI":"10.1109\/MM.2008.48"},{"key":"25","article-title":"Reducing memory interference in multicore systems via application-Aware memory channel partitioning","author":"prashanth","year":"2011","journal-title":"MICRO-44"},{"doi-asserted-by":"publisher","key":"26","DOI":"10.1145\/1736020.1736045"},{"doi-asserted-by":"publisher","key":"27","DOI":"10.1145\/2155620.2155624"},{"key":"28","article-title":"MARSSx86: A full system simulator for x86 CPUs","author":"avadh","year":"2011","journal-title":"DAC"},{"key":"29","doi-asserted-by":"crossref","first-page":"32","DOI":"10.1145\/360128.360134","article-title":"A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality","author":"zhang","year":"2000","journal-title":"MICRO33 Proceedings of the 33rd Annual ACM\/IEEE International Symposium on Microarchitecture"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/ISCA.2008.7"},{"key":"2","article-title":"Atlas: A scalable and high-performance scheduling algorithm for multiple memory controllers","author":"kim","year":"2010","journal-title":"HPCA-16"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/MICRO.2007.21"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/MICRO.2010.51"},{"year":"2004","author":"kopytov","journal-title":"Sysbench A system performance benchmark","key":"30"},{"key":"7","article-title":"Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems","author":"ausavarungnirun","year":"2012","journal-title":"ISCA"},{"key":"6","article-title":"Reducing memory interference in multicore systems via application-Aware memory channel partitioning","author":"prashanth","year":"2011","journal-title":"MICRO-44"},{"doi-asserted-by":"publisher","key":"32","DOI":"10.1016\/j.jpdc.2010.08.020"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/MICRO.2007.21"},{"doi-asserted-by":"publisher","key":"31","DOI":"10.1109\/ISCA.2004.1310764"},{"key":"4","article-title":"Memory performance attacks: Denial of memory service in multi-core systems","author":"moscibroda","year":"2007","journal-title":"Usenix Security"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/MICRO.2010.51"},{"key":"8","article-title":"ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers","author":"kim","year":"2010","journal-title":"HPCA"}],"event":{"name":"2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)","start":{"date-parts":[[2014,8,20]]},"location":"Chongqing, China","end":{"date-parts":[[2014,8,22]]}},"container-title":["2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6900045\/6910490\/06910521.pdf?arnumber=6910521","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T21:31:48Z","timestamp":1498167108000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6910521\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,8]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1109\/rtcsa.2014.6910521","relation":{},"subject":[],"published":{"date-parts":[[2014,8]]}}}