{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:14:49Z","timestamp":1729620889900,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,7]]},"DOI":"10.1109\/samos.2011.6045469","type":"proceedings-article","created":{"date-parts":[[2011,10,18]],"date-time":"2011-10-18T15:33:32Z","timestamp":1318952012000},"page":"255-262","source":"Crossref","is-referenced-by-count":5,"title":["Breaking the bandwidth wall in chip multiprocessors"],"prefix":"10.1109","author":[{"given":"Augusto","family":"Vega","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Felipe","family":"Cabarcas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alex","family":"Ramirez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mateo","family":"Valero","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555774"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1455650.1455651"},{"key":"ref12","first-page":"1","article-title":"Understanding how off-chip memory bandwidth partitioning in chip multiprocessors affects system performance","author":"liu","year":"2010","journal-title":"Proceedings of the 16th International Symposium on High-Performance Computer Architecture"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.41"},{"key":"ref14","article-title":"The top 10 innovations in the new nvidia fermi architecture, and the top 3 next challenges","author":"patterson","year":"2009","journal-title":"Technical Report NVIDIA"},{"key":"ref15","article-title":"Scalable simulation of decoupled accelerator architectures","author":"rico","year":"2010","journal-title":"Technical Report UPC-DAC-RR-2010–10 University of Catalonia"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555801"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2009.407"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2009.9"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/359842.359858"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1476936.1477008"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1188455.1188546"},{"journal-title":"ITRS International Technology Roadmap for Semiconductors","year":"2006","key":"ref6"},{"journal-title":"Nvidia's Next Generation CUDA Compute Architecture Fermi","year":"0","author":"corp","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555779"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1839676.1839694"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"173","DOI":"10.1535\/itj.1103.01","article-title":"Integration challenges and tradeoffs for tera-scale architectures","volume":"11","author":"azimi","year":"2007","journal-title":"Intel Tech Journal"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.45"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1147\/rd.494.0589"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1013610.807295"},{"key":"ref22","first-page":"71","article-title":"The Power7TM processor SoC","author":"wendel","year":"0","journal-title":"IC Design and Technology (ICICDT) 2010 IEEE International Conference on"},{"journal-title":"Cacti 5 0 Technical Report HPL-2007–167 HP Labs","year":"0","author":"thoziyoor","key":"ref21"}],"event":{"name":"2011 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XI)","start":{"date-parts":[[2011,7,18]]},"location":"Samos, Greece","end":{"date-parts":[[2011,7,21]]}},"container-title":["2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6036614\/6045429\/06045469.pdf?arnumber=6045469","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T08:12:31Z","timestamp":1497946351000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6045469\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,7]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/samos.2011.6045469","relation":{},"subject":[],"published":{"date-parts":[[2011,7]]}}}