{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:18:22Z","timestamp":1729628302188,"version":"3.28.0"},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,7]]},"DOI":"10.1109\/samos.2012.6404167","type":"proceedings-article","created":{"date-parts":[[2013,1,17]],"date-time":"2013-01-17T15:29:49Z","timestamp":1358436589000},"page":"136-143","source":"Crossref","is-referenced-by-count":3,"title":["Automatic FPGA synthesis of memory intensive C-based kernels"],"prefix":"10.1109","author":[{"given":"Matthew","family":"Milford","sequence":"first","affiliation":[]},{"given":"John","family":"McAllister","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Compiler Construction A Recursive Descent Model","year":"1996","author":"elder","key":"19"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/5.381846"},{"journal-title":"Algebraic Semantics of Imperative Programs","year":"1996","author":"jo","key":"18"},{"key":"15","first-page":"279","article-title":"Combining data reuse with data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework","volume":"28","author":"liu","year":"2009","journal-title":"IEEE Trans CAD"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508189"},{"key":"13","first-page":"13","article-title":"Compaan: deriving process networks from Matlab for embedded signal processing architectures","author":"kienhuis","year":"2000","journal-title":"Proceedings of the Eighth International Workshop on Hardware\/Software Codesign CODES 2000 (IEEE Cat No 00TH8518) HSC"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-009-0380-1"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ICIP.2008.4712028"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2004.1339557"},{"key":"21","doi-asserted-by":"crossref","DOI":"10.1201\/b10629","author":"engel","year":"2006","journal-title":"Real-Time Volume Graphics"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2012.6288211"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/78.485935"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"journal-title":"FPGAs for DSP","year":"2008","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/1455229.1455230"},{"journal-title":"SynphonyC Compiler","year":"0","key":"7"},{"journal-title":"Catapult-C","year":"2010","author":"graphics","key":"6"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-6199-6"},{"journal-title":"Virtex-6 FPGA Memory Resources User Guide","year":"2011","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/1176254.1176306"},{"journal-title":"AutoESL High-Level Synthesis Tool","year":"0","key":"8"}],"event":{"name":"2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XII)","start":{"date-parts":[[2012,7,16]]},"location":"Samos, Greece","end":{"date-parts":[[2012,7,19]]}},"container-title":["2012 International Conference on Embedded Computer Systems (SAMOS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6389877\/6404141\/06404167.pdf?arnumber=6404167","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T01:50:45Z","timestamp":1498009845000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6404167\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,7]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/samos.2012.6404167","relation":{},"subject":[],"published":{"date-parts":[[2012,7]]}}}