{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T03:55:48Z","timestamp":1775620548651,"version":"3.50.1"},"reference-count":58,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,7]]},"DOI":"10.1109\/samos.2016.7818353","type":"proceedings-article","created":{"date-parts":[[2017,1,19]],"date-time":"2017-01-19T21:30:13Z","timestamp":1484861413000},"page":"235-244","source":"Crossref","is-referenced-by-count":73,"title":["Coarse grained reconfigurable architectures in the past 25 years: Overview and classification"],"prefix":"10.1109","author":[{"given":"Mark","family":"Wijtvliet","sequence":"first","affiliation":[]},{"given":"Luc","family":"Waeijen","sequence":"additional","affiliation":[]},{"given":"Henk","family":"Corporaal","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","author":"corporaal","year":"1997","journal-title":"Microprocessor Architectures From VLIW to TTA"},{"key":"ref38","article-title":"DART: a dynamically reconfigurable architecture dealing with future mobile telecommunications constraints","author":"david","year":"2003","journal-title":"Résumé"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.2000.903407"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1186\/1687-3963-2007-078082"},{"key":"ref31","doi-asserted-by":"crossref","DOI":"10.1023\/A:1008159121620","article-title":"Design methodology of a low-energy reconfigurable single-chip DSP system","volume":"28","author":"wan","year":"2001","journal-title":"Journal of VLSI Signal Processing Systems for Signal Image and Video Technology"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/4.881217"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2002.1106783"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.21236\/ADA419598"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2000.854393"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"key":"ref28","article-title":"REMARC: Reconfigurable multimedia array coprocessor","author":"miyamori","year":"1999","journal-title":"IEICE Transactions on Information and Systems"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/2.839324"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296444"},{"key":"ref2","article-title":"Configurable logic cell tips n tricks","year":"0"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815968"},{"key":"ref20","article-title":"Colt: An experiment in wormhole run-time reconfiguration","year":"1996","journal-title":"Photonics East Conference on High-Speed Computing Digital Signal Processing and Filtering Using FPGAs"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ARVLSI.1999.756035"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1996.564808"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1997.624600"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707889"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201314"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/2.612254"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311262"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2008.08.007"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412155"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0775"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2014.12"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.51"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2044667"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/1629395.1629433"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669160"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2386883"},{"key":"ref11","author":"gaillardon","year":"2015","journal-title":"Reconfigurable Logic Architecture Tools and Applications ser Devices Circuits and Systems"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1023\/A:1024499601571"},{"key":"ref12","author":"groeneveld","year":"1993","journal-title":"Ocean The Sea-of-Gates design system"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.5120\/7429-0104","article-title":"Survey on coarse grained reconfigurable architectures","author":"tehre","year":"2012","journal-title":"International Journal of Computer Applications"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/980152.980156"},{"key":"ref15","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-540-45234-8_7","article-title":"Adres: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix","author":"mei","year":"2003","journal-title":"Field Programmable Logic and Application"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/4.92017"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/4.173120"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HICSS.1993.270747"},{"key":"ref19","article-title":"A datapath synthesis system for the reconfigurable datapath architecture","author":"hartenstein","year":"1995","journal-title":"Design Automation Conference 1995 Proceedings of the ASP-DAC'95\/CHDL'95\/VLSI'95 IFIP International Conference on Hardware Description Languages IFIP International Conference on Very Large Scal"},{"key":"ref4","article-title":"The industrys first floating-point FPGA","year":"0"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853195"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SC.Companion.2012.93"},{"key":"ref5","article-title":"Position paper: Reaching intrinsic compute efficiency requires adaptable micro-architectures","author":"wijtvliet","year":"2016","journal-title":"Programmability and Architectures for Heterogeneous Multicores MULTIPROG 2016 Ninth International Workshop on"},{"key":"ref8","author":"sutter","year":"0","journal-title":"Handbook of Signal Processing Systems"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339272"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/43.898829"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915091"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1524\/itit.2007.49.3.157"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311311"},{"key":"ref48","article-title":"Going beyond the FPGA with spacetime","year":"0"},{"key":"ref47","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-540-30117-2_48","article-title":"ch. Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases","author":"amano","year":"2004","journal-title":"Field Programmable Logic and Application 14th International Conference FPL 2004 Leuven Belgium August 30-September 1 2004 Proceedings"},{"key":"ref42","article-title":"Design and evaluation of a coarse-grained reconfigurable architecture","author":"kim","year":"2004","journal-title":"Proc ISOCC"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/1233307.1233308"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126605002659"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-27776-7_36"}],"event":{"name":"2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)","location":"Agios Konstantinos, Samos Island, Greece","start":{"date-parts":[[2016,7,17]]},"end":{"date-parts":[[2016,7,21]]}},"container-title":["2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7803477\/7818316\/07818353.pdf?arnumber=7818353","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,17]],"date-time":"2019-09-17T15:46:32Z","timestamp":1568735192000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7818353\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,7]]},"references-count":58,"URL":"https:\/\/doi.org\/10.1109\/samos.2016.7818353","relation":{},"subject":[],"published":{"date-parts":[[2016,7]]}}}