{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T15:30:06Z","timestamp":1759332606634,"version":"3.28.0"},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,7]]},"DOI":"10.1109\/samos.2017.8344605","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T23:33:43Z","timestamp":1524526423000},"page":"1-10","source":"Crossref","is-referenced-by-count":7,"title":["Exploring different execution paradigms in exposed datapath architectures with buffered processing units"],"prefix":"10.1109","author":[{"given":"Anoop","family":"Bhagyanath","sequence":"first","affiliation":[]},{"given":"Klaus","family":"Schneider","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"299","article-title":"Code generation for STA architecture","author":"guo","year":"2006","journal-title":"International Conference on Parallel Processing J -L Baer and L Snyder Eds"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2009.6"},{"key":"ref12","first-page":"77","article-title":"Towards code generation for the synchronous control asynchronous dataflow (SCAD) architectures","author":"bhagyanath","year":"2016","journal-title":"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation Von Schaltungen Und Systemen"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2016.7797759"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ACSD.2017.20"},{"key":"ref15","first-page":"337","article-title":"Z3: An efficient SMT solver","volume":"4963","author":"mendon\u00e7a","year":"2008","journal-title":"Tools and Algorithms for the Construction and Analysis of Systems Ser LNCS"},{"journal-title":"SCAD processor simulator","year":"0","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325117"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0105108"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.2002.1106670"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/321607.321620"},{"key":"ref3","first-page":"248","article-title":"Clock rate versus IPC: the end of the road for conventional microarchitectures","author":"agarwal","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/40.653013"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2007.15"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2006.10"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291018"},{"journal-title":"Embedded Computing A VLIW Approach to Architecture Compilers and Tools","year":"2005","author":"fisher","key":"ref2"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1147\/rd.111.0025","article-title":"An efficient algorithm for exploiting multiple arithmetic units","volume":"11","author":"tomasulo","year":"1967","journal-title":"IBM Journal of Research and Development"},{"key":"ref9","article-title":"Integer linear programming-based scheduling for transport triggered architectures","volume":"12","author":"\u00e4ij\u00f6","year":"2015","journal-title":"ACM Transactions on Architecture and Code Optimization"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1233307.1233308"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2011.6045474"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1016\/S1383-7621(98)00046-0"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2013.6621141"},{"journal-title":"Drinking from the firehose The belt machine model in the MillTM CPU architectures","year":"2013","author":"godard","key":"ref23"}],"event":{"name":"2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)","start":{"date-parts":[[2017,7,17]]},"location":"Pythagorion","end":{"date-parts":[[2017,7,20]]}},"container-title":["2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337645\/8344598\/08344605.pdf?arnumber=8344605","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T05:48:05Z","timestamp":1643176085000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8344605\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/samos.2017.8344605","relation":{},"subject":[],"published":{"date-parts":[[2017,7]]}}}