{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T13:20:35Z","timestamp":1730294435216,"version":"3.28.0"},"reference-count":34,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,7]]},"DOI":"10.1109\/samos.2017.8344643","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T23:33:43Z","timestamp":1524526423000},"page":"292-299","source":"Crossref","is-referenced-by-count":0,"title":["Access-aware DRAM failure-rate estimation under relaxed refresh operations"],"prefix":"10.1109","author":[{"given":"Konstantinos","family":"Tovletoglou","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dimitrios S.","family":"Nikolopoulos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Georgios","family":"Karakonstantis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Intel","article-title":"How to Benchmark Code Execution Times on Intel IA-32 and IA-64 Instruction Set Architectures","year":"2010","key":"ref33"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1250734.1250746"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2003.1191551"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804101"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522336"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446096"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485929"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/CASES.2015.7324549"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950391"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/2.585157"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2014.96"},{"key":"ref19","doi-asserted-by":"crossref","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","author":"binkert","year":"2011","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref28","first-page":"5","article-title":"Memprof: A memory profiler for numa multicore systems","author":"lachaize","year":"2012","journal-title":"Proceedings of the 2012 USENIX Conference on Annual Technical Conference ser USENIX ATC'12"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840883"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485927"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594295"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/16.678551"},{"journal-title":"DINAMITE A modern approach to memory performance profiling","year":"2016","author":"miucin","key":"ref29"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.177"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598122"},{"key":"ref7","first-page":"1","article-title":"RAIDR: Retention-aware intelligent dram refresh","author":"liu","year":"2012","journal-title":"Proceedings of the 39th Annual International Symposium on Computer Architecture Ser ISCA '12"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1250880"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.13"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"365","DOI":"10.1145\/2024723.2000108","article-title":"Dark silicon and the end of multicore scaling","volume":"39","author":"esmaeilzadeh","year":"2011","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485928"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2009.2023248"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2417540"},{"key":"ref24","doi-asserted-by":"crossref","first-page":"235","DOI":"10.1145\/2872887.2750408","article-title":"Flexible auto-refresh","volume":"43","author":"bhati","year":"2015","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2905002"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428043"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2597652.2597663"}],"event":{"name":"2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)","start":{"date-parts":[[2017,7,17]]},"location":"Pythagorion","end":{"date-parts":[[2017,7,20]]}},"container-title":["2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337645\/8344598\/08344643.pdf?arnumber=8344643","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T07:49:43Z","timestamp":1643183383000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8344643\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7]]},"references-count":34,"URL":"https:\/\/doi.org\/10.1109\/samos.2017.8344643","relation":{},"subject":[],"published":{"date-parts":[[2017,7]]}}}