{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T08:49:51Z","timestamp":1725612591035},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,7]]},"DOI":"10.1109\/sasp.2009.5226330","type":"proceedings-article","created":{"date-parts":[[2009,9,2]],"date-time":"2009-09-02T09:41:09Z","timestamp":1251884469000},"page":"15-20","source":"Crossref","is-referenced-by-count":2,"title":["A dataflow-centric approach to design low power control paths in CGRAs"],"prefix":"10.1109","author":[{"given":"Hyunchul","family":"Park","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yongjun","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Scott","family":"Mahlke","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"2001","journal-title":"TMS320C55x DSP CPU Programmer's Guide","key":"17"},{"doi-asserted-by":"publisher","key":"15","DOI":"10.1109\/40.464580"},{"doi-asserted-by":"publisher","key":"16","DOI":"10.1109\/MM.2002.997877"},{"doi-asserted-by":"publisher","key":"13","DOI":"10.1145\/192724.192731"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1145\/1216544.1216550"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/ISCA.1990.134511"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/DATE.2004.1269235"},{"key":"3","doi-asserted-by":"crossref","DOI":"10.1145\/1165573.1165646","article-title":"power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture","author":"kim","year":"2006","journal-title":"Proc of the 2006 International Symposium on Low Power Electronics and Design"},{"key":"2","first-page":"66","article-title":"architecture enhancements for the adres coarse-grained reconfigurable array","author":"bouwens","year":"2008","journal-title":"Proc of the 2008 International Conference on High Performance Embedded Architectures and Compilers"},{"key":"1","first-page":"363","article-title":"a spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures","author":"ahn","year":"2006","journal-title":"Proc of Design Automation and Test in Europe Mar 2006"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1145\/502239.502244"},{"key":"7","first-page":"727","article-title":"the morphosys parallel reconfigurable system","author":"lu","year":"1999","journal-title":"Proc International Euro-Par Conference"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/DAC.1995.250017"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/MICRO.1997.645810"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/VLSI.2008.25"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/FPL.2005.1515799"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/DATE.2003.1253623"}],"event":{"name":"2009 IEEE 7th Symposium on Application Specific Processors (SASP)","start":{"date-parts":[[2009,7,27]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2009,7,28]]}},"container-title":["2009 IEEE 7th Symposium on Application Specific Processors"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5209559\/5226326\/05226330.pdf?arnumber=5226330","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T19:24:00Z","timestamp":1497813840000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5226330\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,7]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/sasp.2009.5226330","relation":{},"subject":[],"published":{"date-parts":[[2009,7]]}}}