{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T01:13:24Z","timestamp":1725412404184},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,7]]},"DOI":"10.1109\/sasp.2009.5226344","type":"proceedings-article","created":{"date-parts":[[2009,9,2]],"date-time":"2009-09-02T09:41:09Z","timestamp":1251884469000},"page":"101-106","source":"Crossref","is-referenced-by-count":3,"title":["Dynamic and application-driven I-cache partitioning for low-power embedded multitasking"],"prefix":"10.1109","author":[{"given":"Mathew","family":"Paul","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peter","family":"Petrov","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2004.1349307"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645830"},{"key":"14","article-title":"cacti 5.1","author":"ahn","year":"2008","journal-title":"Technical Report HP Laboratories"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/92.920821"},{"key":"12","first-page":"148","article-title":"drowsy caches: simple techniques for reducing leakage power","author":"flautner","year":"2002","journal-title":"ISCA"},{"key":"3","doi-asserted-by":"crossref","first-page":"234","DOI":"10.1145\/1278480.1278537","article-title":"a self-tuning configurable cache","author":"gordon-ross","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809463"},{"key":"1","article-title":"reconfigurable caches and their application to media processing","author":"ranganathan","year":"2000","journal-title":"ISCA-25"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2005.13"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391545"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1289881.1289917"},{"key":"4","first-page":"136","article-title":"a highly configurable cache architecture for embedded systems","author":"zhang","year":"2003","journal-title":"ISCA"},{"key":"9","first-page":"402","article-title":"exploiting program hotspots and code sequentiality for instruction cache leakage management","author":"hu","year":"2003","journal-title":"ISLPED"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118482"}],"event":{"name":"2009 IEEE 7th Symposium on Application Specific Processors (SASP)","start":{"date-parts":[[2009,7,27]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2009,7,28]]}},"container-title":["2009 IEEE 7th Symposium on Application Specific Processors"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5209559\/5226326\/05226344.pdf?arnumber=5226344","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T19:24:00Z","timestamp":1497813840000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5226344\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,7]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/sasp.2009.5226344","relation":{},"subject":[],"published":{"date-parts":[[2009,7]]}}}