{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,17]],"date-time":"2025-09-17T14:56:26Z","timestamp":1758120986979,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/sbcci.2003.1232815","type":"proceedings-article","created":{"date-parts":[[2004,1,24]],"date-time":"2004-01-24T04:33:03Z","timestamp":1074918783000},"page":"111-116","source":"Crossref","is-referenced-by-count":6,"title":["FPGA-based hardware architecture for neural networks: binary radix vs. stochastic"],"prefix":"10.1109","author":[{"given":"N.","family":"Nedjah","sequence":"first","affiliation":[]},{"given":"Lde.M.","family":"Mourelle","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"A stochastic neural architecture that exploits dynamically reconfigurable FPGAs Proceedings IEEE Workshop on FPGAs for Custom Computing Machines","year":"1993","author":"daalen","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/12.954506"},{"journal-title":"Xilinx Inc","year":"0","key":"ref10"},{"key":"ref6","first-page":"37","author":"gaines","year":"0","journal-title":"Stochastic Computing Systems Advances in Information Systems Science"},{"key":"ref5","first-page":"80","volume":"29","author":"daalen","year":"1993","journal-title":"A device for generating binary sequence for stochastic computing Electronics Letters"},{"journal-title":"Neural Network Adaptation to Hardware Implementations In Fiesler E and Beale Reds Handbook of Neural Computation","year":"1996","author":"moerland","key":"ref8"},{"journal-title":"Fundamentals of Artificial Neural Networks","year":"1995","author":"hassoun","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/12.954505"},{"journal-title":"VHDL Analysis and Modeling of Digital Systems","year":"1998","author":"navabi","key":"ref9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1994.315612"}],"event":{"name":"16th Symposium on Integrated Circuits and Systems Design. SBCCI 2003","acronym":"SBCCI-03","location":"Sao Paulo, Brazil"},"container-title":["16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8726\/27627\/01232815.pdf?arnumber=1232815","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T18:41:35Z","timestamp":1489430495000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1232815\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/sbcci.2003.1232815","relation":{},"subject":[]}}