{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:17:47Z","timestamp":1729628267959,"version":"3.28.0"},"reference-count":21,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/sbcci.2003.1232818","type":"proceedings-article","created":{"date-parts":[[2004,1,23]],"date-time":"2004-01-23T23:33:03Z","timestamp":1074900783000},"page":"131-136","source":"Crossref","is-referenced-by-count":0,"title":["A fast IP-core integration methodology for SoC design"],"prefix":"10.1109","author":[{"given":"J.Ad.'O.","family":"Filho","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.E.","family":"de Lima","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.R.","family":"Maciel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Moura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B.","family":"Celso","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.1997.587178"},{"journal-title":"Synthesis of self-timed VLSI circuits from graph-theoretic specifications","year":"1987","author":"chu","key":"ref11"},{"key":"ref12","first-page":"25","article-title":"and M. AVCl","author":"uzam","year":"2001","journal-title":"Digital Hardware Implementation of Petri Net Based Specifications Direct Translation from Safe Automation Petri Nets to Circuit Elements"},{"key":"ref13","first-page":"307","author":"jung","year":"1994","journal-title":"Direct Synthesis of Efficient Speed-independent Circuits from Deterministic Signal Transition Graphs"},{"key":"ref14","first-page":"541","volume":"44","author":"murata","year":"0","journal-title":"Petri Nets Properties Analysis and Applications"},{"journal-title":"Concurrent Hardware The Theory and Practice of Self-Timed Design Series in Parallel Computing","year":"1994","author":"kishinevsky","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511526558"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.1997.587178"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/43.644602"},{"journal-title":"proceedings of IEEE International Conference on Computer Aided Design 96","year":"0","author":"chung","key":"ref4"},{"article-title":"A New Interface Specification Methodology and its Application to Transducer Synthesis","year":"1988","author":"borriello","key":"ref3"},{"journal-title":"Interfacing Incompatible Protocols using Interface Process Generation 32nd ACM\/IEEE Design Automation Conference","year":"1995","author":"gajski","key":"ref6"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"8","DOI":"10.1145\/277044.277047","article-title":"Automatic synthesis of interfaces between incompatible protocols","author":"passerone","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"key":"ref8","first-page":"44","author":"de jong","year":"1994","journal-title":"A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules"},{"key":"ref7","first-page":"101","author":"lin","year":"1994","journal-title":"Synthesis of Concurrent System Interface Modules with Automatic Protocol Conversion Generation"},{"journal-title":"Hardware and Petri Nets Application to Asynchronous Circuit Design","year":"2000","author":"cortadella","key":"ref2"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1007\/3-540-65307-4_49","article-title":"Petri Nets and Digital Hardware Design","volume":"1492","author":"yakovlev","year":"1998","journal-title":"Lectures on Petri Nets II Applications Lecture Notes in Computer Science"},{"year":"0","key":"ref21"},{"journal-title":"AMBA 2 0 Specification","year":"0","key":"ref24"},{"journal-title":"AVALON Bus Specification - Reference Manual version 2 0","year":"2002","key":"ref23"},{"journal-title":"QUARTUS II Manual","year":"0","key":"ref25"}],"event":{"name":"16th Symposium on Integrated Circuits and Systems Design. SBCCI 2003","acronym":"SBCCI-03","location":"Sao Paulo, Brazil"},"container-title":["16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8726\/27627\/01232818.pdf?arnumber=1232818","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T23:18:34Z","timestamp":1497568714000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1232818\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/sbcci.2003.1232818","relation":{},"subject":[]}}