{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:39:32Z","timestamp":1773247172400,"version":"3.50.1"},"reference-count":27,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,9]]},"DOI":"10.1109\/sbcci.2013.6644864","type":"proceedings-article","created":{"date-parts":[[2013,10,31]],"date-time":"2013-10-31T00:12:39Z","timestamp":1383178359000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Delay model for static CMOS complex gates"],"prefix":"10.1109","author":[{"given":"Felipe S.","family":"Marranghello","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andre I.","family":"Reis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Renato P.","family":"Ribas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.847892"},{"key":"17","first-page":"1","article-title":"Modeling the overshooting effect of multi-input gate innanometer technologies","author":"ding","year":"2011","journal-title":"Proc of IEEE Int'l Midwest Symp OnCircuits and Systems (MWSCAS)"},{"key":"18","author":"sutherland","year":"1999","journal-title":"Logical Effort Designing FastCMOS Circuits"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/81.795832"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/4.736655"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2005.851992"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/4.68126"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/43.317470"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/43.759070"},{"key":"21","first-page":"634","article-title":"Delay estimation and sizing of CMOS;ogic using logical effort with slope correction","volume":"56","author":"wang","year":"2009","journal-title":"IEEE IEEE Trans Circuits Syst II Exp Briefs"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.857400"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/43.391734"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/4.346"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052168"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/43.992767"},{"key":"26","first-page":"3829","article-title":"Energy model of CMOS gatesusing a piecewise linear model","author":"liu","year":"2010","journal-title":"Proc of IEEE Int'l Symp OnCircuits and Systems (ISCAS)"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/4.52187"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270271"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/43.35557"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/1228784.1228857"},{"key":"7","doi-asserted-by":"crossref","first-page":"250","DOI":"10.1109\/TCAD.2009.2035539","article-title":"Modeling the overshooting effect for CMOSinverter delay analysis in nanometer technologies","volume":"29","author":"zhangcai","year":"2010","journal-title":"IEEE Trans Comput -Aided Des Integr Circuits Syst"},{"key":"6","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/SBCCI.2012.6344424","article-title":"Design-oriented delay modelfor CMOS inverter","author":"marranghello","year":"2012","journal-title":"Proc Symp Integrated Circuits and Systems Design (SBCCI)"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.830692"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/4.293109"},{"key":"9","first-page":"516","article-title":"A timing analysis tool for VLSI CMOSsynchronous circuits","author":"uebel","year":"1996","journal-title":"Proc of IEEE Int'l Symp on Circuits AndSystems (ISCAS)"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1063\/1.1697872"}],"event":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","location":"Curitiba, Brazil","start":{"date-parts":[[2013,9,2]]},"end":{"date-parts":[[2013,9,6]]}},"container-title":["2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6634599\/6644849\/06644864.pdf?arnumber=6644864","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T01:07:35Z","timestamp":1498093655000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6644864\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/sbcci.2013.6644864","relation":{},"subject":[],"published":{"date-parts":[[2013,9]]}}}