{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:37:29Z","timestamp":1729629449953,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,9]]},"DOI":"10.1109\/sbcci.2013.6644872","type":"proceedings-article","created":{"date-parts":[[2013,10,30]],"date-time":"2013-10-30T20:12:39Z","timestamp":1383163959000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Analytical logical effort formulation for minimum active area under delay constraints"],"prefix":"10.1109","author":[{"given":"Caio G. P.","family":"Alegretti","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vinicius","family":"Dal Bem","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Renato P.","family":"Ribas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andre I.","family":"Reis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1997.597189"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.927758"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.920087"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1287\/opre.1050.0254"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/43.851993"},{"key":"13","doi-asserted-by":"crossref","first-page":"511","DOI":"10.1109\/ISQED.2002.996796","article-title":"Timing and design closure in physical design flows","author":"coudert","year":"2002","journal-title":"InProc Int Symposium on Quality Electronic Design ISQED"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/92.645073"},{"year":"0","key":"11"},{"key":"12","doi-asserted-by":"crossref","first-page":"818","DOI":"10.1109\/TCAD.2009.2015735","article-title":"Gate sizing for cell-library-baseddesigns","volume":"28","author":"hu","year":"2009","journal-title":"Computer-Aided Design of IntegratedCircuits and Systems IEEE Transactions on"},{"year":"0","key":"21"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2000.835124"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.927758"},{"key":"23","first-page":"777","article-title":"KL-Cuts: A newapproach for logic synthesis targeting multiple output blocks","author":"martinello","year":"0","journal-title":"DATE2010"},{"key":"24","first-page":"1","article-title":"KL-cutbased digital circuit remapping","author":"machado","year":"0","journal-title":"NORCHIP 2012"},{"key":"25","article-title":"Iterativeremapping respecting timing constraints","author":"machado","year":"2013","journal-title":"Accepted for ISVLSI"},{"key":"26","article-title":"Logic synthesis for manufacturability considering regularity andlithography printability","author":"machado","year":"2013","journal-title":"Accepted for ISVLSI"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.847892"},{"journal-title":"Logical Effort Designing FastCMOS Circuits","year":"1999","author":"sutherland","key":"2"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.895793"},{"key":"1","first-page":"1","article-title":"Logical effort: Designing for speedon the back of an envelope","author":"sutherland","year":"1991","journal-title":"Proc Univ California\/Santa Cruz Conf Adv Res VLSI"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2010.02.002"},{"key":"6","first-page":"703","article-title":"Cell stack length using an enhancedlogical effort model for a library-free paradigm","author":"el-masry","year":"2011","journal-title":"Proc IEEE Int Conf Electronics Circuits and Systems"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2024245"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.857400"},{"key":"9","first-page":"983","article-title":"Standard cell library optimization forleakage reduction","author":"shah","year":"2006","journal-title":"Proc Design Automation Conf"},{"key":"8","first-page":"178","article-title":"Optimal p\/n width ratio selection forstandard cell libraries","author":"kung","year":"1999","journal-title":"Proc Int Conf on Computer Aided Design"}],"event":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","start":{"date-parts":[[2013,9,2]]},"location":"Curitiba, Brazil","end":{"date-parts":[[2013,9,6]]}},"container-title":["2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6634599\/6644849\/06644872.pdf?arnumber=6644872","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T21:07:34Z","timestamp":1498079254000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6644872\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/sbcci.2013.6644872","relation":{},"subject":[],"published":{"date-parts":[[2013,9]]}}}