{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T18:40:53Z","timestamp":1725475253978},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,8]]},"DOI":"10.1109\/sbcci.2018.8533263","type":"proceedings-article","created":{"date-parts":[[2018,11,15]],"date-time":"2018-11-15T21:32:18Z","timestamp":1542317538000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template"],"prefix":"10.1109","author":[{"given":"Felipe A.","family":"Kuentzer","sequence":"first","affiliation":[]},{"given":"Leonardo R.","family":"Juracy","sequence":"additional","affiliation":[]},{"given":"Matheus T.","family":"Moreira","sequence":"additional","affiliation":[]},{"given":"Alexandre M.","family":"Amory","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934600"},{"journal-title":"Plasma CPU","year":"2014","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168949"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.289"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488771"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007148"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2016.9"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2328658"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/12.2252"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1023\/A:1024687809014"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.190"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2220912"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2015.13"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2418713"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2014.21"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2365878"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523226"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2536179"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2589548"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2010.44"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2005.5"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2006.40"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2930670"}],"event":{"name":"2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI)","start":{"date-parts":[[2018,8,27]]},"location":"Bento Goncalves","end":{"date-parts":[[2018,8,31]]}},"container-title":["2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8513831\/8533220\/08533263.pdf?arnumber=8533263","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T15:45:53Z","timestamp":1643211953000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8533263\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,8]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/sbcci.2018.8533263","relation":{},"subject":[],"published":{"date-parts":[[2018,8]]}}}