{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T13:16:56Z","timestamp":1730294216912,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,9,2]],"date-time":"2024-09-02T00:00:00Z","timestamp":1725235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,9,2]],"date-time":"2024-09-02T00:00:00Z","timestamp":1725235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,9,2]]},"DOI":"10.1109\/sbcci62366.2024.10704004","type":"proceedings-article","created":{"date-parts":[[2024,10,9]],"date-time":"2024-10-09T17:45:03Z","timestamp":1728495903000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["Drift of Combinational Circuits Failure Rates with a Probabilistic Model Approximated by Partitioning"],"prefix":"10.1109","author":[{"given":"Esther","family":"Goudet","sequence":"first","affiliation":[{"name":"IPParis Crolles &amp; Palaiseau,STMicroelectronics Crolles, LTCI, T&#x00E9;l&#x00E9;com Paris,France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luis H. Pe\u00f1a","family":"Trevi\u00f1o","sequence":"additional","affiliation":[{"name":"IPParis Crolles &amp; Palaiseau,STMicroelectronics Crolles, LTCI, T&#x00E9;l&#x00E9;com Paris,France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gutemberg Goncalves","family":"Dos Santos","sequence":"additional","affiliation":[{"name":"Federal Univ. of Campina Grande Campina Grande,VIRTUS RDI Center,Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sayah","family":"El Hajji","sequence":"additional","affiliation":[{"name":"Univ. de Rennes, CNRS, IPR Crolles &amp; Rennes,STMicroelectronics Crolles,France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fabio","family":"Sureau","sequence":"additional","affiliation":[{"name":"STMicroelectronics Crolles,Crolles,France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lirida","family":"Naviner","sequence":"additional","affiliation":[{"name":"IPParis Palaiseau,LTCI, T&#x00E9;l&#x00E9;com Paris,France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean-Marc","family":"Daveau","sequence":"additional","affiliation":[{"name":"STMicroelectronics Crolles,Crolles,France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philippe","family":"Roche","sequence":"additional","affiliation":[{"name":"STMicroelectronics Crolles,Crolles,France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS48227.2022.9764426"},{"year":"2018","key":"ref2","article-title":"Road vehicles - functional safety"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/LATS58125.2023.10154491"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2008.4606383"},{"key":"ref5","first-page":"1","article-title":"Fast and accurate estimation of correctness rate in combinatorial circuits based on clustering","volume-title":"the 19th IEEE Workshop on Silicon Errors in Logic \u2013 System Effects (SELSE)","author":"Goudet"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2008.4674942"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2008.4616787"},{"key":"ref8","first-page":"59","article-title":"Evaluating circuit reliability under probabilistic gate-level fault models","volume-title":"the International Workshop on Logic and Synthesis (IWLS)","author":"Patel"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.47"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1137\/1.9781611976472.1"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1137\/18M1176865"},{"key":"ref12","article-title":"k-way hypergraph partitioning via n-level recursive bisection","volume-title":"CoRR","volume":"abs\/1511.03137","author":"Schlag"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1201\/9781420010749.ch61"},{"key":"ref14","article-title":"Buddy c++ library"},{"key":"ref15","article-title":"Iscas\u201985, iscas\u201989, itc\u201999\/iscas\u201999 and 74x-series netlists"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2011.06.017"}],"event":{"name":"2024 37th SBC\/SBMicro\/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI)","start":{"date-parts":[[2024,9,2]]},"location":"Joao Pessoa, Brazil","end":{"date-parts":[[2024,9,6]]}},"container-title":["2024 37th SBC\/SBMicro\/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10703968\/10703870\/10704004.pdf?arnumber=10704004","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,10]],"date-time":"2024-10-10T11:27:34Z","timestamp":1728559654000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10704004\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,9,2]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/sbcci62366.2024.10704004","relation":{},"subject":[],"published":{"date-parts":[[2024,9,2]]}}}