{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T01:13:29Z","timestamp":1740100409260,"version":"3.37.3"},"reference-count":23,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,11,22]],"date-time":"2021-11-22T00:00:00Z","timestamp":1637539200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,11,22]],"date-time":"2021-11-22T00:00:00Z","timestamp":1637539200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,11,22]],"date-time":"2021-11-22T00:00:00Z","timestamp":1637539200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100005674","name":"Funda\u00e7\u00e3o de Desenvolvimento da Pesquisa","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100005674","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,11,22]]},"DOI":"10.1109\/sbesc53686.2021.9628309","type":"proceedings-article","created":{"date-parts":[[2021,12,6]],"date-time":"2021-12-06T21:15:42Z","timestamp":1638825342000},"page":"1-8","source":"Crossref","is-referenced-by-count":1,"title":["Implementation and Evaluation of Adaptive Cache Insertion Policies for Real-Time Systems"],"prefix":"10.1109","author":[{"given":"Bruna Arruda","family":"Araujo","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giovani","family":"Gracioli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tomasz","family":"Kloda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Denis","family":"Hoornaert","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marco","family":"Caccamo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Computer Organization and Architecture Designing for Performance","year":"2009","author":"stallings","key":"ref10"},{"journal-title":"Structured Computer Organization","year":"2005","author":"tanenbaum","key":"ref11"},{"journal-title":"Preliminary discussion of the logical design of an electronic computing instrument","year":"1946","author":"burks","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.5"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2392987.2393009"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346202"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2014.6925997"},{"key":"ref17","first-page":"17:1","article-title":"Impact of DM-LRU on WCET: A Static Analysis Approach","volume":"133","author":"mancuso","year":"2019","journal-title":"ECRTS 2019"},{"key":"ref18","first-page":"1:1","article-title":"Deterministic Memory Abstraction and Supporting Multicore System Architecture","volume":"106","author":"farshchi","year":"2018","journal-title":"ECRTS 2018"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2013.6732205"},{"journal-title":"Computer Architecture Fifth Edition A Quantitative Approach","year":"2011","author":"hennessy","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-007-9032-3"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2016.0114"},{"journal-title":"Valgrind 3 3 - Advanced Debugging and Profiling for GNU\/Linux Applications","year":"2008","author":"seward","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2830555"},{"key":"ref1","first-page":"27:1","article-title":"Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms","volume":"133","author":"gracioli","year":"2019","journal-title":"ECRTS 2019"},{"journal-title":"Computer Organization and Design The Hardware\/Software Interface Fourth Edition","year":"2013","author":"patterson","key":"ref9"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2014.6983043"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/321738.321743"},{"key":"ref21","first-page":"6","article-title":"Techniques For The Synthesis Of Multiprocessor Tasksets","author":"emberson","year":"2010","journal-title":"WATERS at the ECRTS ’10"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-007-9012-7"}],"event":{"name":"2021 XI Brazilian Symposium on Computing Systems Engineering (SBESC)","start":{"date-parts":[[2021,11,22]]},"location":"Florianopolis, Brazil","end":{"date-parts":[[2021,11,26]]}},"container-title":["2021 XI Brazilian Symposium on Computing Systems Engineering (SBESC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9628149\/9628198\/09628309.pdf?arnumber=9628309","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:54:03Z","timestamp":1652201643000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9628309\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11,22]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/sbesc53686.2021.9628309","relation":{},"subject":[],"published":{"date-parts":[[2021,11,22]]}}}