{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:59:43Z","timestamp":1780675183881,"version":"3.54.1"},"reference-count":48,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,11,1]],"date-time":"2022-11-01T00:00:00Z","timestamp":1667260800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,11,1]],"date-time":"2022-11-01T00:00:00Z","timestamp":1667260800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100006231","name":"Brookhaven National Laboratory","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006231","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,11]]},"DOI":"10.1109\/sc41404.2022.00084","type":"proceedings-article","created":{"date-parts":[[2023,2,23]],"date-time":"2023-02-23T18:38:40Z","timestamp":1677177520000},"page":"1-15","source":"Crossref","is-referenced-by-count":7,"title":["Scalable Deep Learning-Based Microarchitecture Simulation on GPUs"],"prefix":"10.1109","author":[{"given":"Santosh","family":"Pandey","sequence":"first","affiliation":[{"name":"Stevens Institute of Technology,Hoboken,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lingda","family":"Li","sequence":"additional","affiliation":[{"name":"Brookhaven National Laboratory,Upton,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Thomas","family":"Flynn","sequence":"additional","affiliation":[{"name":"Brookhaven National Laboratory,Upton,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Adolfy","family":"Hoisie","sequence":"additional","affiliation":[{"name":"Brookhaven National Laboratory,Upton,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hang","family":"Liu","sequence":"additional","affiliation":[{"name":"Stevens Institute of Technology,Hoboken,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/885651.781076"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2003.1206991"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3185768.3185771"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2015.29"},{"key":"ref6","first-page":"28","article-title":"CMP$im: A Pin-based On-the-fly Multi-core Cache Simulator","volume-title":"Proceedings of the Fourth Annual Workshop on Modeling, Benchmarking and Simulation (MoBS), co-located with ISCA","author":"Jaleel"},{"key":"ref7","first-page":"1050","article-title":"MARSS: A Full System Simulator for Multicore x86 CPUs","volume-title":"48th ACM\/EDAC\/IEEE Design Automation Conference (DAC)","author":"Patel"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.4018\/jdst.2010040104"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485963"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/239912.239923"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903263"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.58"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835956"},{"key":"ref15","first-page":"4505","article-title":"Ithemal: Accurate, Portable and Fast Basic Block Throughput Estimation Using Deep Neural Networks","volume-title":"International Conference on Machine Learning (ICML)","author":"Mendis"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3530891"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.5555\/2999134.2999257"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.917757"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/SC41405.2020.00060"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2021.3090316"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2021.3064892"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485963"},{"key":"ref24","first-page":"91","article-title":"Sniper: Scalable and Accurate Parallel Multi-core Simulation","volume-title":"8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES)","author":"Heirman"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1071690.1064278"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416636"},{"key":"ref27","article-title":"QEMU, A Fast and Portable Dynamic Translator","volume-title":"USENIX annual technical conference, FREENIX Track","volume":"41","author":"Bellard"},{"key":"ref28","volume-title":"NVIDIA A100 Tensor Core GPU Architecture","year":"2021"},{"key":"ref29","volume-title":"TensorRT","year":"2021"},{"key":"ref30","article-title":"Accelerating Sparse Deep Neural Networks","author":"Mishra","year":"2021","journal-title":"arXiv preprint"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/HICSS.1994.323171"},{"key":"ref32","volume-title":"SUMMIT Oak Ridge National Laboratorys 200 Petaflop Supercomputer","author":"Ridge","year":"2020"},{"key":"ref33","volume-title":"Evaluating gem5 and qemu Virtual Platforms for ARM Multi-core Architectures","author":"Morales","year":"2016"},{"key":"ref34","article-title":"Evaluation of the Riken Post-k Processor Simulator","author":"Kodama","year":"2019","journal-title":"arXiv preprint"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555775"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-7566-5"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00014"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2002.8"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/12.689650"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168882"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346211"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/1229428.1229479"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056063"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830780"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2014.30"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/3126557"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/samos.2015.7363659"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897977"}],"event":{"name":"SC22: International Conference for High Performance Computing, Networking, Storage and Analysis","location":"Dallas, TX, USA","start":{"date-parts":[[2022,11,13]]},"end":{"date-parts":[[2022,11,18]]}},"container-title":["SC22: International Conference for High Performance Computing, Networking, Storage and Analysis"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10046045\/10045783\/10046116.pdf?arnumber=10046116","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,13]],"date-time":"2024-02-13T17:23:35Z","timestamp":1707845015000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10046116\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,11]]},"references-count":48,"URL":"https:\/\/doi.org\/10.1109\/sc41404.2022.00084","relation":{},"subject":[],"published":{"date-parts":[[2022,11]]}}}